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Date:   Tue, 19 Jul 2022 18:53:25 +0100
From:   Mark Brown <broonie@kernel.org>
To:     "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@amd.com>
Cc:     Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>,
        "p.yadav@ti.com" <p.yadav@ti.com>,
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Subject: Re: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI
 device
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On Tue, Jul 19, 2022 at 01:21:41PM +0000, Mahapatra, Amit Kumar wrote:

> I agree, so for checking the controller multiple chip select capability(u=
sing=20
> more than one chip select at once) we can define a new spi controller DT=
=20
> property like "multi-cs-cap"(please suggest a better name).=20
> The controller that can support multiple chip selects should have this pr=
operty=20
> in the spi controller DT node. The spi core will check ctlr->multi-cs-cap=
 to=20
> operate multiple chip select in parallel.

I'm not sure this needs to be a DT property, it's more just something we
infer from the compatible.  The name seems fine, as does the flag in the
controller data.

> > the chip selects are available and that the controller can do something=
 useful
> > with them (and probably have an implementation in the core for doing so=
 via
> > GPIO).

> Here are you referring to the usecase in which a controller implementing =
multi CS
> support using GPIO? =20

Yes, we probably ought to.

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