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From:   Rob Herring <robh+dt@kernel.org>
Date:   Wed, 20 Jul 2022 11:40:40 -0600
Message-ID: <CAL_Jsq+H+nzacGEZ4TRgZ70jUHugpNj=jpA+XfaWjhuduH1GLA@mail.gmail.com>
Subject: Re: [PATCH 2/2] PCI: mvebu: add support for orion5x
To:     =?UTF-8?Q?Pali_Roh=C3=A1r?= <pali@kernel.org>
Cc:     Arnd Bergmann <arnd@arndb.de>,
        Mauri Sandberg <maukka@ext.kapsi.fi>,
        linux-pci <linux-pci@vger.kernel.org>,
        DTML <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Andrew Lunn <andrew@lunn.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        Gregory CLEMENT <gregory.clement@bootlin.com>,
        Russell King - ARM Linux <linux@armlinux.org.uk>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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On Wed, Jul 20, 2022 at 10:13 AM Pali Roh=C3=A1r <pali@kernel.org> wrote:
>
> On Tuesday 19 July 2022 12:16:34 Arnd Bergmann wrote:
> > On Tue, Jul 19, 2022 at 11:46 AM Pali Roh=C3=A1r <pali@kernel.org> wrot=
e:
> > > On Tuesday 19 July 2022 10:05:28 Arnd Bergmann wrote:
> > > > > +/* Relevant only for Orion-1/Orion-NAS */
> > > > > +#define ORION5X_PCIE_WA_PHYS_BASE      0xf0000000
> > > > > +#define ORION5X_PCIE_WA_VIRT_BASE      IOMEM(0xfd000000)
> > > >
> > > > You should not need to hardcode these here. The ORION5X_PCIE_WA_PHY=
S_BASE
> > > > should already be part of the DT binding.
> > >
> > > Of course! But the issue is that we do not know how to do this DT
> > > binding. I have already wrote email with asking for help in which
> > > property and which format should be this config range defined, but no
> > > answer yet: https://lore.kernel.org/linux-pci/20220710225108.bgedria6=
igtqpz5l@pali/
> >
> > Ah, I had not seen that email. Quoting from there:
> >
> > > So my question is: How to properly define config space range in devic=
e
> > > tree file? In which device tree property and in which format? Please
> > > note that this memory range of config space is PCIe root port specifi=
c
> > > and it requires its own MBUS_ID() like memory range of PCIe MEM and P=
CIe
> > > IO mapping. Please look e.g. at armada-385.dtsi how are MBUS_ID() use=
d:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tr=
ee/arch/arm/boot/dts/armada-385.dtsi
> >
> > This is probably a question for Rob as the mvebu driver is a rather spe=
cial
> > case. Normally this would just be a 'reg' property of the host bridge,
> > but I think
> > in your case the root device is imaginary, and the ports under it are t=
he
> > actual hardware devices
>
> yes
>
> > so you'll probably have to do the same thing as
> > the armada-385, translating the mbus ranges for the config space in the
> > "ranges" property of the parent
>
> Problem is that "ranges" in PCIe are used for specifying MEM and IO
> mappings and kernel PCI code does not allow any other type.

The kernel does not, but the binding does (well, the original OF PCI
bus supplement does, but the schema currently does not). If there's a
real need to support config space in ranges, then we can relax the
constraints.

Rob