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From:   <Kavyasree.Kotagiri@microchip.com>
To:     <Horatiu.Vultur@microchip.com>
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Subject: RE: [PATCH 2/2] ARM: dts: lan966x: add support for pcb8309
Thread-Topic: [PATCH 2/2] ARM: dts: lan966x: add support for pcb8309
Thread-Index: AQHYnHFivQ+9+83cwEOVN6Agi6GAea2IVJeg
Date:   Thu, 21 Jul 2022 06:08:46 +0000
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References: <20220720194904.2025384-1-horatiu.vultur@microchip.com>
 <20220720194904.2025384-3-horatiu.vultur@microchip.com>
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> Add basic support for pcb8309. It is similar with pcb8291 with one big
> difference that is having 2 SFP cages. Therefore it has 4 network ports.
>=20
> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
> ---
>  arch/arm/boot/dts/Makefile            |   3 +-
>  arch/arm/boot/dts/lan966x-pcb8309.dts | 189
> ++++++++++++++++++++++++++
>  2 files changed, 191 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/lan966x-pcb8309.dts
>=20
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 184899808ee7..6a6166e3a405 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -772,7 +772,8 @@ dtb-$(CONFIG_SOC_IMXRT) +=3D \
>  dtb-$(CONFIG_SOC_LAN966) +=3D \
>  	lan966x-pcb8291.dtb \
>  	lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
> -	lan966x-kontron-kswitch-d10-mmt-8g.dtb
> +	lan966x-kontron-kswitch-d10-mmt-8g.dtb \
> +	lan966x-pcb8309.dtb
>  dtb-$(CONFIG_SOC_LS1021A) +=3D \
>  	ls1021a-iot.dtb \
>  	ls1021a-moxa-uc-8410a.dtb \
> diff --git a/arch/arm/boot/dts/lan966x-pcb8309.dts
> b/arch/arm/boot/dts/lan966x-pcb8309.dts
> new file mode 100644
> index 000000000000..ef441195e8c1
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x-pcb8309.dts
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * lan966x_pcb8309.dts - Device Tree file for PCB8309
> + */
> +/dts-v1/;
> +#include "lan966x.dtsi"
> +#include "dt-bindings/phy/phy-lan966x-serdes.h"
> +
> +/ {
> +	model =3D "Microchip EVB - LAN9662";
> +	compatible =3D "microchip,lan9662-pcb8309", "microchip,lan9662",
> "microchip,lan966";
> +
> +	aliases {
> +		serial0 =3D &usart3;
> +		i2c102 =3D &i2c102;
> +		i2c103 =3D &i2c103;
> +	};
> +
> +	chosen {
> +		stdout-path =3D "serial0:115200n8";
> +	};
> +
> +	gpio-restart {
> +		compatible =3D "gpio-restart";
> +		gpios =3D <&gpio 56 GPIO_ACTIVE_LOW>;
> +		priority =3D <200>;
> +	};
> +
> +	i2c-mux {
> +		compatible =3D "i2c-mux";
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +		mux-controls =3D <&mux>;
> +		i2c-parent =3D <&i2c4>;
> +
> +		i2c102: i2c-sfp@1 {
> +			reg =3D <1>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;

Why do you need #address-cells and #size-cells here?
> +		};
> +
> +		i2c103: i2c-sfp@2 {
> +			reg =3D <2>;
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;
Same here
> +		};
> +	};
> +
> +	mux: mux-controller {
> +		compatible =3D "gpio-mux";
> +		#mux-control-cells =3D <0>;
> +
> +		mux-gpios =3D <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /*
> p11b0 */
> +			    <&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1
> */
> +	};
> +
> +	sfp2: sfp2 {
> +		compatible =3D "sff,sfp";
> +		i2c-bus =3D <&i2c102>;
> +		tx-disable-gpios =3D <&sgpio_out 10 0 GPIO_ACTIVE_LOW>;
> +		los-gpios =3D <&sgpio_in  2 0 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpios =3D <&sgpio_in  2 1 GPIO_ACTIVE_LOW>;
> +		tx-fault-gpios =3D <&sgpio_in  1 0 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	sfp3: sfp3 {
> +		compatible =3D "sff,sfp";
> +		i2c-bus =3D <&i2c103>;
> +		tx-disable-gpios =3D <&sgpio_out 10 1 GPIO_ACTIVE_LOW>;
> +		los-gpios =3D <&sgpio_in  3 0 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpios =3D <&sgpio_in  3 1 GPIO_ACTIVE_LOW>;
> +		tx-fault-gpios =3D <&sgpio_in  1 1 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +&flx3 {
> +	atmel,flexcom-mode =3D <ATMEL_FLEXCOM_MODE_USART>;
> +	status =3D "okay";
> +
> +	usart3: serial@200 {
> +		pinctrl-0 =3D <&fc3_b_pins>;
> +		pinctrl-names =3D "default";
> +		status =3D "okay";
> +	};
> +};
> +
> +&flx4 {
> +	atmel,flexcom-mode =3D <ATMEL_FLEXCOM_MODE_TWI>;
> +	status =3D "okay";
> +};
> +
> +&gpio {
> +	fc3_b_pins: fc3-b-pins {
> +		/* RXD, TXD */
> +		pins =3D "GPIO_52", "GPIO_53";
> +		function =3D "fc3_b";
> +	};
> +
> +	fc4_b_pins: fc4-b-pins {
> +		/* SCL, SDA */
> +		pins =3D "GPIO_57", "GPIO_58";
> +		function =3D "fc4_b";
> +	};
> +
> +	sgpio_a_pins: sgpio-a-pins {
> +		/* SCK, D0, D1, LD */
> +		pins =3D "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
> +		function =3D "sgpio_a";
> +	};
> +};
> +
> +&i2c4 {
> +	compatible =3D "microchip,sam9x60-i2c";
> +	reg =3D <0x600 0x200>;
> +	interrupts =3D <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> +	#address-cells =3D <1>;
> +	#size-cells =3D <0>;

Same here=20

> +	clocks =3D <&nic_clk>;
> +	pinctrl-0 =3D <&fc4_b_pins>;
> +	pinctrl-names =3D "default";
> +	i2c-analog-filter;
> +	i2c-digital-filter;
> +	i2c-digital-filter-width-ns =3D <35>;
> +	i2c-sda-hold-time-ns =3D <1500>;
> +	status =3D "okay";
> +};
> +
> +&mdio1 {
> +	status =3D "okay";
> +};
> +
> +&phy0 {
> +	status =3D "okay";
> +};
> +
> +&phy1 {
> +	status =3D "okay";
> +};
> +
> +&port0 {
> +	status =3D "okay";
> +	phy-handle =3D <&phy0>;
> +	phy-mode =3D "gmii";
> +	phys =3D <&serdes 0 CU(0)>;
> +};
> +
> +&port1 {
> +	status =3D "okay";
> +	phy-handle =3D <&phy1>;
> +	phy-mode =3D "gmii";
> +	phys =3D <&serdes 1 CU(1)>;
> +};
> +
> +&port2 {
> +	status =3D "okay";
> +	sfp =3D <&sfp2>;
> +	managed =3D "in-band-status";
> +	phy-mode =3D "sgmii";
> +	phys =3D <&serdes 2 SERDES6G(0)>;
> +};
> +
> +&port3 {
> +	status =3D "okay";
> +	sfp =3D <&sfp3>;
> +	managed =3D "in-band-status";
> +	phy-mode =3D "sgmii";
> +	phys =3D <&serdes 3 SERDES6G(1)>;
> +};
> +
> +&serdes {
> +	status =3D "okay";
> +};
> +
> +&sgpio {
> +	status =3D "okay";
> +	pinctrl-0 =3D <&sgpio_a_pins>;
> +	pinctrl-names =3D "default";
> +	microchip,sgpio-port-ranges =3D <0 3>, <8 11>;
> +	gpio@0 {
> +		ngpios =3D <64>;
> +	};
> +	gpio@1 {
> +		ngpios =3D <64>;
> +	};
> +};
> +
> +&switch {
> +	status =3D "okay";
> +};
> --
> 2.33.0