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From:   "Yuan, Perry" <Perry.Yuan@amd.com>
To:     "Huang, Ray" <Ray.Huang@amd.com>
CC:     "rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
        "viresh.kumar@linaro.org" <viresh.kumar@linaro.org>,
        "Sharma, Deepak" <Deepak.Sharma@amd.com>,
        "Limonciello, Mario" <Mario.Limonciello@amd.com>,
        "Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
        "Deucher, Alexander" <Alexander.Deucher@amd.com>,
        "Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
        "Huang, Shimmer" <Shimmer.Huang@amd.com>,
        "Du, Xiaojian" <Xiaojian.Du@amd.com>,
        "Meng, Li (Jassmine)" <Li.Meng@amd.com>,
        "linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v4 02/13] cpufreq: amd-pstate: enable AMD Precision Boost
 mode switch
Thread-Topic: [PATCH v4 02/13] cpufreq: amd-pstate: enable AMD Precision Boost
 mode switch
Thread-Index: AQHYmDJW/S+tkgXJIU2NUQanxupnxq2E4VwAgAOyAZA=
Date:   Thu, 21 Jul 2022 09:15:29 +0000
Message-ID: <DM4PR12MB5278690EC137B90714DE7C079C919@DM4PR12MB5278.namprd12.prod.outlook.com>
References: <cover.1657876961.git.Perry.Yuan@amd.com>
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[AMD Official Use Only - General]

Hi Ray.=20

> -----Original Message-----
> From: Huang, Ray <Ray.Huang@amd.com>
> Sent: Tuesday, July 19, 2022 8:46 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>
> Cc: rafael.j.wysocki@intel.com; viresh.kumar@linaro.org; Sharma, Deepak
> <Deepak.Sharma@amd.com>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Su, Jinzhou (Joe) <Jinzhou.Su@amd.com>;
> Huang, Shimmer <Shimmer.Huang@amd.com>; Du, Xiaojian
> <Xiaojian.Du@amd.com>; Meng, Li (Jassmine) <Li.Meng@amd.com>; linux-
> pm@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v4 02/13] cpufreq: amd-pstate: enable AMD Precision B=
oost
> mode switch
>=20
> On Fri, Jul 15, 2022 at 06:04:21PM +0800, Yuan, Perry wrote:
> > Add support to switch AMD precision boost state to scale cpu max
> > frequency that will help to improve the processor throughput.
> >
> > when set boost state to be enabled, user will need to execute below
> > commands, the CPU will reach absolute maximum performance level or the
> > highest perf which CPU physical support. This performance level may
> > not be sustainable for long durations, it will help to improve the IO w=
orkload
> tasks.
> >
> > * turn on CPU boost state under root
> >   echo 1 > /sys/devices/system/cpu/cpufreq/boost
> >
> > If user set boost off,the CPU can reach to the maximum sustained
> > performance level of the process, that level is the process can
> > maintain continously working and definitely it can save some power
> > compared to boost on mode.
> >
> > * turn off CPU boost state under root
> >   echo 0 > /sys/devices/system/cpu/cpufreq/boost
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> >  arch/x86/include/asm/msr-index.h |  2 ++
> >  drivers/cpufreq/amd-pstate.c     | 22 +++++++++++++++++++---
> >  2 files changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/x86/include/asm/msr-index.h
> > b/arch/x86/include/asm/msr-index.h
> > index 869508de8269..b952fd6d6916 100644
> > --- a/arch/x86/include/asm/msr-index.h
> > +++ b/arch/x86/include/asm/msr-index.h
> > @@ -559,6 +559,8 @@
> >  #define AMD_CPPC_MIN_PERF(x)		(((x) & 0xff) << 8)
> >  #define AMD_CPPC_DES_PERF(x)		(((x) & 0xff) << 16)
> >  #define AMD_CPPC_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)
> > +#define AMD_CPPC_PRECISION_BOOST_BIT	25
> > +#define AMD_CPPC_PRECISION_BOOST_ENABLED
> 	BIT_ULL(AMD_CPPC_PRECISION_BOOST_BIT)
>=20
> The bit 25 (CpbDis) of MSRC001_0015 [Hardware Configuration] indicates th=
e
> core performance boost disable flag.
>=20
> Please see the section 17.2 Core Performance Boost of PPR:
>=20
> https://www.amd.com/system/files/TechDocs/40332.pdf
>=20
> Core performance boost (CPB) dynamically monitors processor activity to c=
reate
> an estimate of power consumption. If the estimated processor consumption =
is
> below an internally defined power limit and software has requested P0 on =
a
> given core, hardware may transition the core to a frequency and voltage b=
eyond
> those defined for P0. If the estimated power consumption exceeds the defi=
ned
> power limit, some or all cores are limited to the frequency and voltage d=
efined
> by P0.
>=20
> The boost state is designed for legacy ACPI P-State function which is to =
request
> higher frequency beyond P0 State (it's equal to nominal frequency in CPPC=
), and
> we already have the operation like MSR_K7_HWCR_CPB_DIS in acpi-cpufreq
> driver. However, in CPPC, we can modify the performance hint beyond the
> nominal perf to reach the goal. That won't need this control anymore. And
> furthermore, this function for legacy ACPI P-State should not be mixed th=
em up
> with CPPC policy. We should prevent the effect for this flag in CPPC.
>=20
> Thanks,
> Ray

I did not notice that acpi_cpufreq already use this bit to control performa=
nce boost.
Seems like the patch is not needed for CPPC like you said.
I will drop the patch in V5 and use target perf to get target perf to firmw=
are.=20
That will also do the same thing to limit the perf level and power consumpt=
ion.

Thanks for your feedback. Will send V5 soon.

Perry .

>=20
> >
> >  /* AMD Performance Counter Global Status and Control MSRs */
> >  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS	0xc0000300
> > diff --git a/drivers/cpufreq/amd-pstate.c
> > b/drivers/cpufreq/amd-pstate.c index 9ac75c1cde9c..188e055e24a2 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -122,6 +122,7 @@ struct amd_cpudata {
> >
> >  	u64 freq;
> >  	bool	boost_supported;
> > +	u64 	cppc_hw_conf_cached;
> >  };
> >
> >  static inline int pstate_enable(bool enable) @@ -438,18 +439,27 @@
> > static int amd_pstate_set_boost(struct cpufreq_policy *policy, int
> > state)  {
> >  	struct amd_cpudata *cpudata =3D policy->driver_data;
> >  	int ret;
> > +	u64 value;
> >
> >  	if (!cpudata->boost_supported) {
> >  		pr_err("Boost mode is not supported by this processor or
> SBIOS\n");
> >  		return -EINVAL;
> >  	}
> >
> > -	if (state)
> > +	ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (state) {
> > +		value |=3D AMD_CPPC_PRECISION_BOOST_ENABLED;
> >  		policy->cpuinfo.max_freq =3D cpudata->max_freq;
> > -	else
> > +	} else {
> > +		value &=3D ~AMD_CPPC_PRECISION_BOOST_ENABLED;
> >  		policy->cpuinfo.max_freq =3D cpudata->nominal_freq;
> > -
> > +	}
> >  	policy->max =3D policy->cpuinfo.max_freq;
> > +	WRITE_ONCE(cpudata->cppc_hw_conf_cached, value);
> > +	wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, value);
> >
> >  	ret =3D freq_qos_update_request(&cpudata->req[1],
> >  				      policy->cpuinfo.max_freq);
> > @@ -478,6 +488,7 @@ static int amd_pstate_cpu_init(struct cpufreq_polic=
y
> *policy)
> >  	int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
> >  	struct device *dev;
> >  	struct amd_cpudata *cpudata;
> > +	u64 value;
> >
> >  	dev =3D get_cpu_device(policy->cpu);
> >  	if (!dev)
> > @@ -542,6 +553,11 @@ static int amd_pstate_cpu_init(struct
> > cpufreq_policy *policy)
> >
> >  	policy->driver_data =3D cpudata;
> >
> > +	ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_HW_CTL, &value);
> > +	if (ret)
> > +		return ret;
> > +	WRITE_ONCE(cpudata->cppc_hw_conf_cached, value);
> > +
> >  	amd_pstate_boost_init(cpudata);
> >
> >  	return 0;
> > --
> > 2.32.0
> >