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References: <20220712231328.5294-1-kirill.shutemov@linux.intel.com> <20220712231328.5294-3-kirill.shutemov@linux.intel.com>
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From:   Alexander Potapenko <glider@google.com>
Date:   Thu, 21 Jul 2022 15:10:47 +0200
Message-ID: <CAG_fn=U55CSG=xQ8-0Rj9eXrS29n-DiLdCZbqSSRdqiWW9o0fQ@mail.gmail.com>
Subject: Re: [PATCHv5 02/13] x86: CPUID and CR3/CR4 flags for Linear Address Masking
To:     "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc:     Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        "the arch/x86 maintainers" <x86@kernel.org>,
        Kostya Serebryany <kcc@google.com>,
        Andrey Ryabinin <ryabinin.a.a@gmail.com>,
        Andrey Konovalov <andreyknvl@gmail.com>,
        Taras Madan <tarasmadan@google.com>,
        Dmitry Vyukov <dvyukov@google.com>,
        "H . J . Lu" <hjl.tools@gmail.com>,
        Andi Kleen <ak@linux.intel.com>,
        Rick Edgecombe <rick.p.edgecombe@intel.com>,
        Linux Memory Management List <linux-mm@kvack.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Wed, Jul 13, 2022 at 1:13 AM Kirill A. Shutemov
<kirill.shutemov@linux.intel.com> wrote:
>
> Enumerate Linear Address Masking and provide defines for CR3 and CR4
> flags.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

Reviewed-by: Alexander Potapenko <glider@google.com>
Tested-by: Alexander Potapenko <glider@google.com>


> ---
>  arch/x86/include/asm/cpufeatures.h          | 1 +
>  arch/x86/include/uapi/asm/processor-flags.h | 6 ++++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cp=
ufeatures.h
> index 03acc823838a..6ad5841e087f 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -300,6 +300,7 @@
>  /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 *=
/
>  #define X86_FEATURE_AVX_VNNI           (12*32+ 4) /* AVX VNNI instructio=
ns */
>  #define X86_FEATURE_AVX512_BF16                (12*32+ 5) /* AVX512 BFLO=
AT16 instructions */
> +#define X86_FEATURE_LAM                        (12*32+26) /* Linear Addr=
ess Masking */
>
>  /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
>  #define X86_FEATURE_CLZERO             (13*32+ 0) /* CLZERO instruction =
*/
> diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/inclu=
de/uapi/asm/processor-flags.h
> index c47cc7f2feeb..d898432947ff 100644
> --- a/arch/x86/include/uapi/asm/processor-flags.h
> +++ b/arch/x86/include/uapi/asm/processor-flags.h
> @@ -82,6 +82,10 @@
>  #define X86_CR3_PCID_BITS      12
>  #define X86_CR3_PCID_MASK      (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL))
>
> +#define X86_CR3_LAM_U57_BIT    61 /* Activate LAM for userspace, 62:57 b=
its masked */
> +#define X86_CR3_LAM_U57                _BITULL(X86_CR3_LAM_U57_BIT)
> +#define X86_CR3_LAM_U48_BIT    62 /* Activate LAM for userspace, 62:48 b=
its masked */
> +#define X86_CR3_LAM_U48                _BITULL(X86_CR3_LAM_U48_BIT)
>  #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */
>  #define X86_CR3_PCID_NOFLUSH    _BITULL(X86_CR3_PCID_NOFLUSH_BIT)
>
> @@ -132,6 +136,8 @@
>  #define X86_CR4_PKE            _BITUL(X86_CR4_PKE_BIT)
>  #define X86_CR4_CET_BIT                23 /* enable Control-flow Enforce=
ment Technology */
>  #define X86_CR4_CET            _BITUL(X86_CR4_CET_BIT)
> +#define X86_CR4_LAM_SUP_BIT    28 /* LAM for supervisor pointers */
> +#define X86_CR4_LAM_SUP                _BITUL(X86_CR4_LAM_SUP_BIT)
>
>  /*
>   * x86-64 Task Priority Register, CR8
> --
> 2.35.1
>


--=20
Alexander Potapenko
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