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From:   Vidya Sagar <vidyas@nvidia.com>
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Subject: [PATCH V6 15/16] PCI: tegra194: Extend endpoint mode support
Date:   Thu, 21 Jul 2022 19:50:51 +0530
Message-ID: <20220721142052.25971-16-vidyas@nvidia.com>
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Since only Controller-5 can be used in the endpoint mode in P2972-0000
platform, support is available only for Controller-5. This patch extends
that support by enabling the endpoint mode capable controller during
initialization phase which otherwise is not required if it is only
Controller-5.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V6:
* New addition in V6 based on Bjorn's review comment

 drivers/pci/controller/dwc/pcie-tegra194.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index bac2e1ad0a29..fc373b6efd00 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1650,6 +1650,13 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 		return;
 	}
 
+	ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
+	if (ret) {
+		dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
+			pcie->cid, ret);
+		goto fail_set_ctrl_state;
+	}
+
 	ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
 	if (ret) {
 		dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret);
@@ -1798,6 +1805,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 fail_core_clk_enable:
 	tegra_pcie_bpmp_set_pll_state(pcie, false);
 fail_pll_init:
+	tegra_pcie_bpmp_set_ctrl_state(pcie, false);
+fail_set_ctrl_state:
 	pm_runtime_put_sync(dev);
 }
 
-- 
2.17.1