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To:     Sean Anderson <sean.anderson@seco.com>,
        "David S . Miller" <davem@davemloft.net>,
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        Russell King <linux@armlinux.org.uk>,
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        Shawn Guo <shawnguo@kernel.org>, Vinod Koul <vkoul@kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
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Subject: RE: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
 bindings
Thread-Topic: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
 bindings
Thread-Index: AQHYmJdO9OJQL8uRzkOwnuesK8wAT62I4DBg
Date:   Thu, 21 Jul 2022 14:20:42 +0000
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> -----Original Message-----
> From: Sean Anderson <sean.anderson@seco.com>
> Sent: Saturday, July 16, 2022 1:00
> To: David S . Miller <davem@davemloft.net>; Jakub Kicinski
> <kuba@kernel.org>; Madalin Bucur <madalin.bucur@nxp.com>;
> netdev@vger.kernel.org
> Cc: Paolo Abeni <pabeni@redhat.com>; Eric Dumazet
> <edumazet@google.com>; linux-arm-kernel@lists.infradead.org; Russell
> King <linux@armlinux.org.uk>; linux-kernel@vger.kernel.org; Sean Anderson
> <sean.anderson@seco.com>; Kishon Vijay Abraham I <kishon@ti.com>;
> Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Leo Li
> <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
> <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>;
> devicetree@vger.kernel.org; linux-phy@lists.infradead.org
> Subject: [PATCH net-next v3 46/47] arm64: dts: ls1046ardb: Add serdes
> bindings
>=20
> This adds appropriate bindings for the macs which use the SerDes. The
> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
> no driver for this device (and as far as I know all you can do with the
> 100MHz clocks is gate them), so I have chosen to model it as a single
> fixed clock.
>=20
> Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
> This means that Lane A (what the driver thinks is lane 0) uses pins
> SD1_TX3_P/N.
>=20
> Because this will break ethernet if the serdes is not enabled, enable
> the serdes driver by default on Layerscape.
>=20
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> Please let me know if there is a better/more specific config I can use
> here.
>=20
> (no changes since v1)

My LS1046ARDB hangs at boot with this patch right after the second SerDes i=
s probed,
right before the point where the PCI host bridge is registered. I can get a=
round this
either by disabling the second SerDes node from the device tree, or disabli=
ng
CONFIG_PCI_LAYERSCAPE at build.

I haven't debugged it more but there seems to be an issue here.

>  .../boot/dts/freescale/fsl-ls1046a-rdb.dts    | 34 +++++++++++++++++++
>  drivers/phy/freescale/Kconfig                 |  1 +
>  2 files changed, 35 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> index 7025aad8ae89..4f4dd0ed8c53 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> @@ -26,6 +26,32 @@ aliases {
>  	chosen {
>  		stdout-path =3D "serial0:115200n8";
>  	};
> +
> +	clocks {
> +		clk_100mhz: clock-100mhz {
> +			compatible =3D "fixed-clock";
> +			#clock-cells =3D <0>;
> +			clock-frequency =3D <100000000>;
> +		};
> +
> +		clk_156mhz: clock-156mhz {
> +			compatible =3D "fixed-clock";
> +			#clock-cells =3D <0>;
> +			clock-frequency =3D <156250000>;
> +		};
> +	};
> +};
> +
> +&serdes1 {
> +	clocks =3D <&clk_100mhz>, <&clk_156mhz>;
> +	clock-names =3D "ref0", "ref1";
> +	status =3D "okay";
> +};
> +
> +&serdes2 {
> +	clocks =3D <&clk_100mhz>, <&clk_100mhz>;
> +	clock-names =3D "ref0", "ref1";
> +	status =3D "okay";
>  };
>=20
>  &duart0 {
> @@ -140,21 +166,29 @@ ethernet@e6000 {
>  	ethernet@e8000 {
>  		phy-handle =3D <&sgmii_phy1>;
>  		phy-connection-type =3D "sgmii";
> +		phys =3D <&serdes1 1>;
> +		phy-names =3D "serdes";
>  	};
>=20
>  	ethernet@ea000 {
>  		phy-handle =3D <&sgmii_phy2>;
>  		phy-connection-type =3D "sgmii";
> +		phys =3D <&serdes1 0>;
> +		phy-names =3D "serdes";
>  	};
>=20
>  	ethernet@f0000 { /* 10GEC1 */
>  		phy-handle =3D <&aqr106_phy>;
>  		phy-connection-type =3D "xgmii";
> +		phys =3D <&serdes1 3>;
> +		phy-names =3D "serdes";
>  	};
>=20
>  	ethernet@f2000 { /* 10GEC2 */
>  		fixed-link =3D <0 1 1000 0 0>;
>  		phy-connection-type =3D "xgmii";
> +		phys =3D <&serdes1 2>;
> +		phy-names =3D "serdes";
>  	};
>=20
>  	mdio@fc000 {
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfi=
g
> index fe2a3efe0ba4..9595666213d0 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -43,6 +43,7 @@ config PHY_FSL_LYNX_10G
>  	tristate "Freescale Layerscale Lynx 10G SerDes support"
>  	select GENERIC_PHY
>  	select REGMAP_MMIO
> +	default y if ARCH_LAYERSCAPE
>  	help
>  	  This adds support for the Lynx "SerDes" devices found on various
> QorIQ
>  	  SoCs. There may be up to four SerDes devices on each SoC, and
> each
> --
> 2.35.1.1320.gc452695387.dirty