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[209.85.208.45]) by smtp.gmail.com with ESMTPSA id t25-20020aa7d719000000b0043a6c9e50f4sm1113393edq.29.2022.07.21.07.57.09 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jul 2022 07:57:09 -0700 (PDT) Received: by mail-ed1-f45.google.com with SMTP id w12so2458133edd.13 for ; Thu, 21 Jul 2022 07:57:09 -0700 (PDT) X-Received: by 2002:a5d:5889:0:b0:21d:bccd:38e3 with SMTP id n9-20020a5d5889000000b0021dbccd38e3mr34236872wrf.659.1658415009781; Thu, 21 Jul 2022 07:50:09 -0700 (PDT) MIME-Version: 1.0 References: <1657038556-2231-1-git-send-email-quic_khsieh@quicinc.com> In-Reply-To: From: Doug Anderson Date: Thu, 21 Jul 2022 07:49:55 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v16 0/3] eDP/DP Phy vdda realted function To: Dmitry Baryshkov Cc: Johan Hovold , Kuogee Hsieh , Bjorn Andersson , Vinod Koul , Mark Brown , dri-devel , Rob Clark , Sean Paul , Stephen Boyd , Daniel Vetter , David Airlie , Andy Gross , "Abhinav Kumar (QUIC)" , "Aravind Venkateswaran (QUIC)" , Sankeerth Billakanti , freedreno , linux-arm-msm , LKML , Liam Girdwood , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Thu, Jul 21, 2022 at 6:25 AM Dmitry Baryshkov wrote: > > > This series breaks USB and PCIe for some SC8280XP and SA540P machines > > where the DP PHY regulators are shared with other PHYs whose drivers do > > not request a load. > > I'm trying to understand, why does this series cause the regression. > Previously it would be the DP controller voting on the regulators > load, now it has been moved to the DP/eDP PHYs. I think in the past not many device trees actually hooked up the regulators to the DP/eDP but did hook up the regulators to the PHYs? That means they didn't used to get a regulator_set_load() on them and now they do? It should also be noted that we're now setting the load for a bunch of USB PHYs that we didn't used to set a load on... > > It seems quite likely that changes like this one affects other systems > > too, and the effects may be hard to debug. So a more general solution > > than playing whack-a-mole using DT would be good to have. > > I think enabling a regulator which supports set_load() and without > load being set should cause a warning, at least with > CONFIG_REGULATOR_DEBUG. WDYT? I'm not a total fan. I'd love to see evidence to the contrary, but I'm a believer that the amount of extra cruft involved with all these regulator_set_load() calls is overkill for most cases. All the extra code / per-SoC tables added to drivers isn't ideal. Every single LDO on Qualcomm's PMICs seems to be able to be set in "high power mode" and "low power mode", but I think the majority of clients only really care about two things: on and in high power mode vs. off. I think the amount of stuff peripherals can do in low power mode is super limited, so you have to be _really_ sure that the peripheral won't draw too much current without you having a chance to reconfigure the regulator. Of course, if the load could be easily specified in the device tree and we could get rid of all the cruft in the drivers then maybe that would be OK. -Doug