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([109.76.125.251]) by smtp.gmail.com with ESMTPSA id e24-20020a05600c219800b003a2cf1535aasm2455697wme.17.2022.07.21.10.21.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 10:21:21 -0700 (PDT) From: Conor Dooley To: u.kleine-koenig@pengutronix.de Cc: conor.dooley@microchip.com, daire.mcnamara@microchip.com, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, lee.jones@linaro.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, robh+dt@kernel.org, thierry.reding@gmail.com Subject: [PATCH v7 0/4] Microchip soft ip corePWM driver Date: Thu, 21 Jul 2022 18:21:06 +0100 Message-Id: <20220721172109.941900-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Conor Dooley Hey Uwe, all, (~same cover as v5) Added some extra patches so I have a cover letter this time. You pointed out that I was overriding npwmcells in the driver and I realised that the dt & binding were not correct so I have added two simple patches to deal with that. The dts patch I will take in my tree once the binding is applied. For the maintainers entry, I mentioned before that I have several changes in-flight for it. We are late~(ish)~ in the cycle so I doubt you'll be applying this for v5.20, but in the off chance you do - I would be happy to send it (with your Ack) alongside an i2c addition that is "deferred". I rebased it ~today~ on top of an additional change so it may not apply for you. In your review of v3, you had a lot of comments about the period and duty cycle calculations, so I have had another run at them. I converted the period calculation to "search" from the bottom up for the suitable prescale value. The duty cycle calculation has been fixed - the problem was exactly what I suspected in my replies to your review. I had to block the use of a 0xFF period_steps register value (which I think should be covered by the updated comment and limitation #2). Beyond that, I have rebased on -next and converted to the devm_ stuff in probe that was recently added & dropped remove() - as requested. I added locking to protect the period racing, changed the #defines and switched to returning -EINVAL when the period is locked to a value greater than that requested. I'll take the dts change myself once the rest is merged. Thanks, Conor. Changes from v6: - Dropped an unused variable that I'd missed - Actually check the return values of the mutex lock()s - Re-rebased on -next for the MAINTAINERS patch (again...) Changes from v5: - switched to a mutex b/c we must sleep with the lock taken - simplified the locking in apply() and added locking to get_state() - reworked apply() as requested - removed the loop in the period calculation (thanks Uwe!) - add a copy of the enable registers in the driver to save on reads. - remove the second (useless) write to sync_update - added some missing rounding in get_state() - couple other minor cleanups as requested in: https://lore.kernel.org/linux-riscv/20220709160206.cw5luo7kxdshoiua@pengutronix.de/ Changes from v4: - dropped some accidentally added files Conor Dooley (4): dt-bindings: pwm: fix microchip corePWM's pwm-cells riscv: dts: fix the icicle's #pwm-cells pwm: add microchip soft ip corePWM driver MAINTAINERS: add pwm to PolarFire SoC entry .../bindings/pwm/microchip,corepwm.yaml | 4 +- MAINTAINERS | 1 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-microchip-core.c | 371 ++++++++++++++++++ 6 files changed, 387 insertions(+), 2 deletions(-) create mode 100644 drivers/pwm/pwm-microchip-core.c base-commit: a3fd3ca134d9485a0f9a7bdcffd7f8bae27f79d3 -- 2.37.1