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This patch depends on [1] to prevent the error below: > > /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o uses soft float > /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn31/dcn31_resource.o > /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn315/dcn315_resource.o uses soft float > /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn315/dcn315_resource.o > /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o uses soft float > /gcc-11.3.0-nolibc/powerpc64-linux/bin/powerpc64-linux-ld: failed to merge target specific data of file drivers/gpu/drm/amd/amdgpu/../display/dc/dcn316/dcn316_resource.o > > [1] https://lore.kernel.org/amd-gfx/20220716195144.342960-1-mwen@igalia.com/ > > Reported-by: Guenter Roeck > Signed-off-by: Melissa Wen > --- > drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 5 +++-- > .../gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 5 +++-- > .../gpu/drm/amd/display/dc/dcn316/dcn316_resource.c | 5 +++-- > drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 11 +++++++++++ > drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h | 3 +++ > 5 files changed, 23 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c > index 178d40c0d70a..929b712cbada 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c > @@ -1663,11 +1663,12 @@ int dcn31_populate_dml_pipes_from_context( > pipes[pipe_cnt].pipe.src.immediate_flip = true; > pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; > pipes[pipe_cnt].pipe.src.gpuvm = true; > - pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; > - pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; > pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; > pipes[pipe_cnt].pipe.src.dcc_rate = 3; > pipes[pipe_cnt].dout.dsc_input_bpc = 0; > + DC_FP_START(); > + dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); > + DC_FP_END(); > > if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) > pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active; > diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c > index df2abd8fe2eb..1a5f5977f962 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c > @@ -1658,11 +1658,12 @@ static int dcn315_populate_dml_pipes_from_context( > > pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; > pipes[pipe_cnt].pipe.src.gpuvm = true; > - pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; > - pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; > pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; > pipes[pipe_cnt].pipe.src.dcc_rate = 3; > pipes[pipe_cnt].dout.dsc_input_bpc = 0; > + DC_FP_START(); > + dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); > + DC_FP_END(); > > if (pipes[pipe_cnt].dout.dsc_enable) { > switch (timing->display_color_depth) { > diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c > index 070fe10a004e..53dea466348f 100644 > --- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c > @@ -1661,11 +1661,12 @@ static int dcn316_populate_dml_pipes_from_context( > > pipes[pipe_cnt].pipe.src.unbounded_req_mode = false; > pipes[pipe_cnt].pipe.src.gpuvm = true; > - pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; > - pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; > pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; > pipes[pipe_cnt].pipe.src.dcc_rate = 3; > pipes[pipe_cnt].dout.dsc_input_bpc = 0; > + DC_FP_START(); > + dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); > + DC_FP_END(); > > if (pipes[pipe_cnt].dout.dsc_enable) { > switch (timing->display_color_depth) { > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > index facac3daeaca..e36cfa5985ea 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c > @@ -435,8 +435,19 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = { > .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, > }; > > +void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, > + int pipe_cnt) > +{ > + dc_assert_fp_enabled(); > + > + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; > + pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; > +} > + > void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) > { > + dc_assert_fp_enabled(); > + > if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { > context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; > context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; > diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h > index 0a10de80c1a4..4372f17b55d4 100644 > --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h > +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h > @@ -31,6 +31,9 @@ > #define DCN3_15_MIN_COMPBUF_SIZE_KB 128 > #define DCN3_16_DEFAULT_DET_SIZE 192 > > +void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, > + int pipe_cnt); > + > void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context); > > void dcn31_calculate_wm_and_dlg_fp( Reviewed-by: Rodrigo Siqueira