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Date:   Thu, 21 Jul 2022 21:16:15 +0200
From:   Greg KH <gregkh@linuxfoundation.org>
To:     kah.jing.lee@intel.com
Cc:     linux-kernel@vger.kernel.org, arnd@arndb.de,
        rafael.j.wysocki@intel.com, tien.sung.ang@intel.com,
        dinh.nguyen@intel.com, Zhou Furong <furong.zhou@intel.com>,
        Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Subject: Re: [PATCH v2 3/3] documentation: misc: intel_sysid: Add the system
 id sysfs documentation for Altera(Intel) FPGA platform
Message-ID: <Ytml/4+F1DANw1Be@kroah.com>
References: <20220721123017.416438-1-kah.jing.lee@intel.com>
 <20220721123258.416802-1-kah.jing.lee@intel.com>
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On Thu, Jul 21, 2022 at 08:32:59PM +0800, kah.jing.lee@intel.com wrote:
> From: Kah Jing Lee <kah.jing.lee@intel.com>
> 
> This sysfs documentation is created for Altera(Intel) FPGA platform
> System ID soft IP. The Altera(Intel) Sysid component is generally
> part of an FPGA design.
> The component can be hotplugged when the FPGA is reconfigured.
> 
> Based on an initial contribution from Ley Foon Tan at Altera
> Signed-off-by: Kah Jing Lee <kah.jing.lee@intel.com>
> Reviewed-by: Zhou Furong <furong.zhou@intel.com>
> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
> ---
>  .../testing/sysfs-devices-platform-soc-sysid  | 27 +++++++++++++++++++
>  1 file changed, 27 insertions(+)
>  create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> 
> diff --git a/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> new file mode 100644
> index 000000000000..9fa58fd88dc0
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-devices-platform-soc-sysid
> @@ -0,0 +1,27 @@
> +What:		/sys/devices/platform/soc@X/soc:base_fpga_region/
> +soc:base_fpga_region:fpga_pr_region0/XXXXXXXX.sysid/
> +Date:		May 2022
> +KernelVersion:	v5.18

5.18 is long released.  And it's after May 2022 now :(


> +Contact:	Kah Jing Lee <kah.jing.lee@intel.com>
> +Description:
> +		The soc@X/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/
> +		XXXXXXXX.sysid/ directory contains read-only attributes exposing
> +		information about an System ID soft IP device. The X values could vary,
> +		based on the FPGA platform System ID soft IP register address.
> +
> +What:		.../XXXXXXX.sysid/sysid
> +Date:		May 2022
> +KernelVersion:	v5.18
> +Contact:	Kah Jing Lee <kah.jing.lee@intel.com>
> +Description:
> +		The .../XXXXXXX.sysid/sysid file contains the System ID for the FPGA
> +		platform which is unique for the platform type and can be used for
> +		checking the platform type for software download purposes.

What format is this data in?

> +
> +What:		.../XXXXXXX.sysid/buildtime
> +Date:		May 2022
> +KernelVersion:	v5.18
> +Contact:	Kah Jing Lee <kah.jing.lee@intel.com>
> +Description:
> +		The .../XXXXXXX.sysid/buildtime file contains the buildtime for the
> +		FPGA board file generation.

What format is this data in?

Please be specific.

thanks,

greg k-h