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Thu, 21 Jul 2022 19:31:35 -0700 (PDT) X-Gm-Message-State: AJIora9QSjYmdVbqnq1gmXXBcwjUVaqpp6KFL0l3+VwjC2JHvrNkxMto bZVUwtsxMp1wpfIkK80cXeDiyvDpGevbFV4EplM= X-Received: by 2002:a1f:9b90:0:b0:374:f09c:876f with SMTP id d138-20020a1f9b90000000b00374f09c876fmr481937vke.12.1658457094710; Thu, 21 Jul 2022 19:31:34 -0700 (PDT) MIME-Version: 1.0 References: <20220704112526.2492342-4-chenhuacai@loongson.cn> <20220705092937.GA552@willie-the-truck> <20220706161736.GC3204@willie-the-truck> <4216f48f-fdf1-ec1e-b963-6f7fe6ba0f63@redhat.com> <20220721095527.GB17088@willie-the-truck> <62d9cb2579602_1f553629442@dwillia2-xfh.jf.intel.com.notmuch> In-Reply-To: <62d9cb2579602_1f553629442@dwillia2-xfh.jf.intel.com.notmuch> From: Huacai Chen Date: Fri, 22 Jul 2022 10:31:21 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V4 3/4] mm/sparse-vmemmap: Generalise vmemmap_populate_hugepages() To: Dan Williams Cc: Will Deacon , David Hildenbrand , Sudarshan Rajagopalan , Huacai Chen , Arnd Bergmann , Thomas Bogendoerfer , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Catalin Marinas , loongarch@lists.linux.dev, linux-arch , Xuefeng Li , Guo Ren , Xuerui Wang , Jiaxun Yang , Andrew Morton , Linux-MM , "open list:MIPS" , LKML , linux-arm-kernel , Feiyang Chen Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Dan, On Fri, Jul 22, 2022 at 5:54 AM Dan Williams wrote: > > Huacai Chen wrote: > > Hi, Will, > > > > On Thu, Jul 21, 2022 at 5:55 PM Will Deacon wrote: > > > > > > On Thu, Jul 21, 2022 at 10:08:10AM +0800, Huacai Chen wrote: > > > > On Wed, Jul 20, 2022 at 5:34 PM David Hildenbrand wrote: > > > > > On 14.07.22 14:34, Huacai Chen wrote: > > > > > > On Fri, Jul 8, 2022 at 5:47 PM Huacai Chen wrote: > > > > > >> On Thu, Jul 7, 2022 at 12:17 AM Will Deacon wrote: > > > > > >>> On Tue, Jul 05, 2022 at 09:07:59PM +0800, Huacai Chen wrote: > > > > > >>>> On Tue, Jul 5, 2022 at 5:29 PM Will Deacon wrote: > > > > > >>>>> On Mon, Jul 04, 2022 at 07:25:25PM +0800, Huacai Chen wrote: > > > > > >>>>>> +int __meminit vmemmap_populate_hugepages(unsigned long start, unsigned long end, > > > > > >>>>>> + int node, struct vmem_altmap *altmap) > > > > > >>>>>> +{ > > > > > >>>>>> + unsigned long addr; > > > > > >>>>>> + unsigned long next; > > > > > >>>>>> + pgd_t *pgd; > > > > > >>>>>> + p4d_t *p4d; > > > > > >>>>>> + pud_t *pud; > > > > > >>>>>> + pmd_t *pmd; > > > > > >>>>>> + > > > > > >>>>>> + for (addr = start; addr < end; addr = next) { > > > > > >>>>>> + next = pmd_addr_end(addr, end); > > > > > >>>>>> + > > > > > >>>>>> + pgd = vmemmap_pgd_populate(addr, node); > > > > > >>>>>> + if (!pgd) > > > > > >>>>>> + return -ENOMEM; > > > > > >>>>>> + > > > > > >>>>>> + p4d = vmemmap_p4d_populate(pgd, addr, node); > > > > > >>>>>> + if (!p4d) > > > > > >>>>>> + return -ENOMEM; > > > > > >>>>>> + > > > > > >>>>>> + pud = vmemmap_pud_populate(p4d, addr, node); > > > > > >>>>>> + if (!pud) > > > > > >>>>>> + return -ENOMEM; > > > > > >>>>>> + > > > > > >>>>>> + pmd = pmd_offset(pud, addr); > > > > > >>>>>> + if (pmd_none(READ_ONCE(*pmd))) { > > > > > >>>>>> + void *p; > > > > > >>>>>> + > > > > > >>>>>> + p = vmemmap_alloc_block_buf(PMD_SIZE, node, altmap); > > > > > >>>>>> + if (p) { > > > > > >>>>>> + vmemmap_set_pmd(pmd, p, node, addr, next); > > > > > >>>>>> + continue; > > > > > >>>>>> + } else if (altmap) > > > > > >>>>>> + return -ENOMEM; /* no fallback */ > > > > > >>>>> > > > > > >>>>> Why do you return -ENOMEM if 'altmap' here? That seems to be different to > > > > > >>>>> what we currently have on arm64 and it's not clear to me why we're happy > > > > > >>>>> with an altmap for the pmd case, but not for the pte case. > > > > > >>>> The generic version is the same as X86. It seems that ARM64 always > > > > > >>>> fallback whether there is an altmap, but X86 only fallback in the no > > > > > >>>> altmap case. I don't know the reason of X86, can Dan Williams give > > > > > >>>> some explaination? > > > > > >>> > > > > > >>> Right, I think we need to understand the new behaviour here before we adopt > > > > > >>> it on arm64. > > > > > >> Hi, Dan, > > > > > >> Could you please tell us the reason? Thanks. > > > > > >> > > > > > >> And Sudarshan, > > > > > >> You are the author of adding a fallback mechanism to ARM64, do you > > > > > >> know why ARM64 is different from X86 (only fallback in no altmap > > > > > >> case)? > > > > > > > > > > I think that's a purely theoretical issue: I assume that in any case we > > > > > care about, the altmap should be reasonably sized and aligned such that > > > > > this will always succeed. > > > > > > > > > > To me it even sounds like the best idea to *consistently* fail if there > > > > > is no more space in the altmap, even if we'd have to fallback to PTE > > > > > (again, highly unlikely that this is relevant in practice). Could > > > > > indicate an altmap-size configuration issue. > > > > > > > > Does David's explanation make things clear? Moreover, I think Dan's > > > > dedicated comments "no fallback" implies that his design is carefully > > > > considered. So I think the generic version using the X86 logic is just > > > > OK. > > > > > > I think the comment isn't worth the metaphorical paper that it's written > > > on! If you can bulk it up a bit based on David's reasoning, then that would > > > help. But yes, I'm happy with the code now, thanks both. > > OK, I will add a detailed comment here. > > Apologies for coming late to the party here, original ping came while I > was on vacation and I only just now noticed the direct questions. All > resolved now or is a question still pending? I updated the patch and added a detailed comment based on David's explanation [1]. If that description is correct, I think there are no more questions. Thank you. [1] https://lore.kernel.org/loongarch/20220721130419.1904711-4-chenhuacai@loongson.cn/T/#u Huacai >