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From:   Avri Altman <Avri.Altman@wdc.com>
To:     Can Guo <quic_cang@quicinc.com>,
        "bvanassche@acm.org" <bvanassche@acm.org>,
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        "linux-scsi@vger.kernel.org" <linux-scsi@vger.kernel.org>,
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CC:     "James E.J. Bottomley" <jejb@linux.ibm.com>,
        "Martin K. Petersen" <martin.petersen@oracle.com>,
        Daejun Park <daejun7.park@samsung.com>,
        Jinyoung Choi <j-young.choi@samsung.com>,
        Kiwoong Kim <kwmad.kim@samsung.com>,
        open list <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 1/2] scsi: ufs: Add Multi-Circular Queue support
Thread-Topic: [PATCH 1/2] scsi: ufs: Add Multi-Circular Queue support
Thread-Index: AQHYmz2OvInxSH8TlUq8qOHvad4nHq2IiDZA
Date:   Fri, 22 Jul 2022 07:31:06 +0000
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References: <1658214120-22772-1-git-send-email-quic_cang@quicinc.com>
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> +static int ufshcd_mcq_config_resource(struct ufs_hba *hba)
> +{
> +       struct platform_device *pdev =3D to_platform_device(hba->dev);
> +       struct ufshcd_res_info_t *res;
> +       struct resource *res_mem, *res_mcq;
> +       int i, ret =3D 0;
> +
> +       memcpy(hba->res, ufshcd_res_info, sizeof(ufshcd_res_info));
> +
> +       for (i =3D 0; i < RES_MAX; i++) {
> +               res =3D &hba->res[i];
> +
> +               res->resource =3D platform_get_resource_byname(pdev,
> +                                                            IORESOURCE_M=
EM,
> +                                                            res->name);
> +               if (!res->resource) {
> +                       dev_info(hba->dev, "Resource %s not provided\n", =
res-
> >name);
> +                       if (i =3D=3D RES_MEM)
> +                               return -ENOMEM;
> +                       continue;
> +               } else if (i =3D=3D RES_MEM) {
> +                       res_mem =3D res->resource;
> +                       res->base =3D hba->mmio_base;
> +                       continue;
> +               }
> +
> +               res->base =3D devm_ioremap_resource(hba->dev, res->resour=
ce);
> +               if (IS_ERR(res->base)) {
> +                       dev_err(hba->dev, "Failed to map res %s, err =3D =
%d\n",
> +                                        res->name, (int)PTR_ERR(res->bas=
e));
> +                       res->base =3D NULL;
> +                       ret =3D PTR_ERR(res->base);
> +                       goto out_err;
> +               }
> +       }
> +
> +       res =3D &hba->res[RES_MCQ];
> +       /* MCQ resource provided */
> +       if (res->base)
> +               goto out;
> +
> +       /* Manually allocate MCQ resource */
Did you consider to force providing the MCQ configuration?

> +       res_mcq =3D res->resource;
> +       res_mcq =3D devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
> +       if (!res_mcq) {
> +               dev_err(hba->dev, "Failed to alloate MCQ resource\n");
> +               goto out_err;
> +       }
> +       res->is_alloc =3D true;
> +
> +       res_mcq->start =3D res_mem->start +
> +                        mcq_sqattr_offset(hba->mcq_capabilities);
> +       res_mcq->end =3D res_mcq->start + 32 * MCQ_QCFG_SIZE - 1;
Shouldn't there can be MCQCap.MAXQ queues and no more than 32?


> +int ufshcd_mcq_init(struct ufs_hba *hba)
> +{
> +       struct Scsi_Host *host =3D hba->host;
> +       struct ufs_hw_queue *hwq;
> +       int i, ret =3D 0;
> +
> +       if (!is_mcq_supported(hba))
> +               return 0;
> +
> +       ret =3D ufshcd_mcq_config_resource(hba);
> +       if (ret) {
> +               dev_err(hba->dev, "Failed to config MCQ resource\n");
> +               return ret;
> +       }
> +
> +       ret =3D ufshcd_vops_config_mcq_rop(hba);
> +       if (ret) {
> +               dev_err(hba->dev, "MCQ Runtime Operation Pointers not
> configured\n");
> +               goto out_err;
> +       }
> +
> +       hba->nr_queues[HCTX_TYPE_DEFAULT] =3D num_possible_cpus();
> +       hba->nr_queues[HCTX_TYPE_READ] =3D 0;
> +       hba->nr_queues[HCTX_TYPE_POLL] =3D 1;
> +
> +       for (i =3D 0; i < HCTX_MAX_TYPES; i++)
> +               host->nr_hw_queues +=3D hba->nr_queues[i];
> +
> +       host->can_queue =3D hba->nutrs;
> +       host->cmd_per_lun =3D hba->nutrs;
> +
> +       /* One more reserved for dev_cmd_queue */
> +       hba->nr_hw_queues =3D host->nr_hw_queues + 1;
Is it possible, since MCQ memory space is *added* to the UTR & UTMR lists,
That we'll keep using the legacy doorbell for query commands?
Wouldn't it will simplify the hw_queue bookkeeping


> -#define ufshcd_hex_dump(prefix_str, buf, len) do {                      =
 \
> -       size_t __len =3D (len);                                          =
  \
> -       print_hex_dump(KERN_ERR, prefix_str,                             =
\
> -                      __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,=
\
> -                      16, 4, buf, __len, false);                        =
\
> +#define ufshcd_hex_dump(prefix_str, buf, len) do {                     \
> +       size_t __len =3D (len);                                          =
 \
> +                                                                       \
> +       print_hex_dump(KERN_ERR, prefix_str,                            \
> +                      __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,=
 \
> +                      16, 4, buf, __len, false);                       \
> +                                                                       \
>  } while (0)
Should this be part of this patch?

> +#define UFSHCD_MCQ_IO_QUEUE_OFFSET     1
Maybe add a comment above: "queue 0 is reserved for query commands" or some=
thing
That is if the query commands don't use the  legacy doorbell

> +static inline bool ufshcd_is_hwq_full(struct ufs_hw_queue *q)
> +{
> +       return (q->sq_hp_slot =3D=3D ((q->sq_tp_slot + 1) %
> +                                     q->max_entries));
> +}
Isn't sq_tp_slot is already % q->max_entries ?


Thanks,
Avri