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Date:   Sun, 24 Jul 2022 08:43:18 +0800
From:   kernel test robot <lkp@intel.com>
To:     =?utf-8?B?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= 
        <zhouyanjie@wanyeetech.com>, tudor.ambarus@microchip.com,
        p.yadav@ti.com, michael@walle.cc, miquel.raynal@bootlin.com,
        richard@nod.at, vigneshr@ti.com, broonie@kernel.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org
Cc:     kbuild-all@lists.01.org, linux-mtd@lists.infradead.org,
        linux-spi@vger.kernel.org, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        aidanmacdonald.0x0@gmail.com, tmn505@gmail.com,
        paul@crapouillou.net, dongsheng.qiu@ingenic.com,
        aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
        jinghui.liu@ingenic.com, sernia.zhou@foxmail.com,
        reimu@sudomaker.com
Subject: Re: [PATCH 3/3] SPI: Ingenic: Add SFC support for Ingenic SoCs.
Message-ID: <202207240839.YeZ8uQ0T-lkp@intel.com>
References: <1658508510-15400-4-git-send-email-zhouyanjie@wanyeetech.com>
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In-Reply-To: <1658508510-15400-4-git-send-email-zhouyanjie@wanyeetech.com>
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Hi "周琰杰,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on broonie-spi/for-next]
[also build test WARNING on mtd/spi-nor/next linus/master v5.19-rc7 next-20220722]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Zhou-Yanjie/Add-SFC-support-for-Ingenic-SoCs/20220723-005011
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20220724/202207240839.YeZ8uQ0T-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/0d9d0e60238025a04d428e64e18211c037229284
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Zhou-Yanjie/Add-SFC-support-for-Ingenic-SoCs/20220723-005011
        git checkout 0d9d0e60238025a04d428e64e18211c037229284
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=alpha SHELL=/bin/bash drivers/spi/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/spi/spi-ingenic-sfc.c: In function 'ingenic_sfc_exec_op_pio':
>> drivers/spi/spi-ingenic-sfc.c:299:16: warning: conversion from 'long unsigned int' to 'u32' {aka 'unsigned int'} changes value from '18446744073709551595' to '4294967275' [-Woverflow]
     299 |         writel(~(INTC_MASK_END | INTC_MASK_RREQ), sfc->base + SFC_REG_INTC);
         |                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/spi/spi-ingenic-sfc.c: In function 'ingenic_sfc_exec_op_dma':
   drivers/spi/spi-ingenic-sfc.c:356:16: warning: conversion from 'long unsigned int' to 'u32' {aka 'unsigned int'} changes value from '18446744073709551599' to '4294967279' [-Woverflow]
     356 |         writel(~INTC_MASK_END, sfc->base + SFC_REG_INTC);
   drivers/spi/spi-ingenic-sfc.c: In function 'ingenic_sfc_poll_status':
   drivers/spi/spi-ingenic-sfc.c:469:16: warning: conversion from 'long unsigned int' to 'u32' {aka 'unsigned int'} changes value from '18446744073709551599' to '4294967279' [-Woverflow]
     469 |         writel(~INTC_MASK_END, sfc->base + SFC_REG_INTC);


vim +299 drivers/spi/spi-ingenic-sfc.c

   267	
   268	static int ingenic_sfc_exec_op_pio(struct ingenic_sfc *sfc, const struct spi_mem_op *op)
   269	{
   270		int ret, val;
   271	
   272		val = readl(sfc->base + SFC_REG_GLB);
   273		u32p_replace_bits(&val, GLB_TRAN_DIR_READ, GLB_TRAN_DIR_MASK);
   274		u32p_replace_bits(&val, GLB_OP_MODE_SLAVE, GLB_OP_MODE_MASK);
   275		writel(val, sfc->base + SFC_REG_GLB);
   276	
   277		val = TRAN_CONF_CMD_EN | op->cmd.opcode;
   278	
   279		if (op->addr.nbytes > 0) {
   280			val |= FIELD_PREP(TRAN_CONF_ADDR_WIDTH_MASK, op->addr.nbytes);
   281	
   282			writel(op->addr.val & 0xffffffff, sfc->base + SFC_REG_DEV_ADDR(0));
   283			writel(op->addr.val >> 32, sfc->base + SFC_REG_DEV_ADDR_PLUS(0));
   284		}
   285	
   286		if (op->dummy.nbytes > 0)
   287			val |= FIELD_PREP(TRAN_CONF_DMY_BITS_MASK,
   288					op->dummy.nbytes * 8 / op->dummy.buswidth);
   289	
   290		if (op->data.nbytes > 0)
   291			val |= TRAN_CONF_DATA_EN;
   292	
   293		writel(val, sfc->base + SFC_REG_TRAN_CONF(0));
   294		writel(op->data.nbytes, sfc->base + SFC_REG_TRAN_LEN);
   295	
   296		ingenic_sfc_set_transfer_mode(sfc, op);
   297	
   298		writel(0x1f, sfc->base + SFC_REG_SCR);
 > 299		writel(~(INTC_MASK_END | INTC_MASK_RREQ), sfc->base + SFC_REG_INTC);
   300	
   301		writel(0, sfc->base + SFC_REG_MEM_ADDR);
   302	
   303		writel(TRIG_FLUSH, sfc->base + SFC_REG_TRIG);
   304		writel(TRIG_START, sfc->base + SFC_REG_TRIG);
   305	
   306		ret = wait_for_completion_timeout(&sfc->completion,
   307				msecs_to_jiffies(INGENIC_SFC_TRANSFER_TIMEOUT));
   308		if (!ret) {
   309			writel(0x1f, sfc->base + SFC_REG_INTC);
   310			writel(0x1f, sfc->base + SFC_REG_SCR);
   311			dev_err(sfc->dev, "line:%d Timeout for ACK from SFC device\n", __LINE__);
   312			return -ETIMEDOUT;
   313		}
   314	
   315		ingenic_sfc_read_rxfifo(sfc, op->data.buf.in, op->data.nbytes);
   316		readl_poll_timeout(sfc->base + SFC_REG_SR, val, val & SR_END, 10, 0);
   317	
   318		writel(INTC_MASK_END | INTC_MASK_RREQ, sfc->base + SFC_REG_SCR);
   319		writel(TRIG_STOP, sfc->base + SFC_REG_TRIG);
   320	
   321		return 0;
   322	}
   323	

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