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Date:   Mon, 25 Jul 2022 19:46:12 +0700
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Subject: Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT
 register
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To:     Paolo Bonzini <pbonzini@redhat.com>, linux-kernel@vger.kernel.org,
        kvm@vger.kernel.org
Cc:     mlevitsk@redhat.com, seanjc@google.com, jon.grimm@amd.com
References: <20220725033428.3699-1-suravee.suthikulpanit@amd.com>
 <4d03f8b0-723c-7ac5-5078-95330e888e60@redhat.com>
From:   Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
In-Reply-To: <4d03f8b0-723c-7ac5-5078-95330e888e60@redhat.com>
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On 7/25/22 4:46 PM, Paolo Bonzini wrote:
> On 7/25/22 05:34, Suravee Suthikulpanit wrote:
>> AMD does not support APIC TSC-deadline timer mode. AVIC hardware
>> will generate GP fault when guest kernel writes 1 to bits [18]
>> of the APIC LVTT register (offset 0x32) to set the timer mode.
>> (Note: bit 18 is reserved on AMD system).
>>
>> Therefore, always intercept and let KVM emulate the MSR accesses.
>>
>> Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception")
>> Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@amd.com>
> 
> Does this fix some kvm-unit-tests testcase?

I am not sure if we have kvm-unit-tests testcases for this.
I found this when enabling tsc-deadline option in QEMU causing
the vm to fail to boot.

> Anyway, I queued the patch, thanks!
> 
> Paolo

Thank you,
Suravee