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From:   Linus Walleij <linus.walleij@linaro.org>
Date:   Mon, 25 Jul 2022 15:54:04 +0200
Message-ID: <CACRpkdaczrU1tM5Yt7P-Q2h+ge8STOi6HvvYeTM-g+JwS8_gZw@mail.gmail.com>
Subject: Re: [PATCH 1/2] gpio: gpio-74x164: add support for CDx4HC4094
To:     Andy Shevchenko <andy.shevchenko@gmail.com>
Cc:     Marcus Folkesson <marcus.folkesson@gmail.com>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Maxime Ripard <mripard@kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Mon, Jul 25, 2022 at 11:32 AM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
> On Thu, Jul 21, 2022 at 11:32 AM Marcus Folkesson
> <marcus.folkesson@gmail.com> wrote:
> >
> > 74hc4094 and 75hc4094 works similar to 74x164 but has an additional
> > storage latch associated with each stage for strobing data from the
> > serial input to parallell buffer tri-state output.
>
> parallel
>
> > Add support for an optional strobe pin.
>
> Sorry for my absence of understanding, but why?
> SPI has MOSI, CLK, CS, where the last one is exactly for that. No?

Forgive me if I misunderstand, but if you use CS that
way, the way that the SPI framework works is to assert
CS then transfer a few chunks over SPI (MOSI/CLK)
then de-assert CS.

If CS is used for strobe, it is constantly asserted
during transfer and the sequence will be latched
out immediately as you write the SPI transfers and
the data is clocked through the register, making the
whole train of zeroes and ones flash across the
output pins before they stabilize after the SPI
transfer is finished.

If you first do the SPI transfer, then strobe after
finished, this will not happen.

Then it should be a separate pin, so this doesn't
happen, right?

Yours,
Linus Walleij