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Message-ID: <ecb58953-4758-3dec-b727-6ab6c8039cbf@quicinc.com>
Date:   Wed, 27 Jul 2022 11:28:21 +0530
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Subject: Re: [PATCH V6 5/5] clk: qcom: lpass: Add support for resets &
 external mclk for SC7280
Content-Language: en-US
To:     Stephen Boyd <sboyd@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Michael Turquette <mturquette@baylibre.com>
CC:     <linux-arm-msm@vger.kernel.org>, <linux-soc@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <robh@kernel.org>,
        <robh+dt@kernel.org>, <quic_tdas@quicinc.com>
References: <1658315023-3336-1-git-send-email-quic_c_skakit@quicinc.com>
 <1658315023-3336-6-git-send-email-quic_c_skakit@quicinc.com>
 <20220727013200.90E37C433C1@smtp.kernel.org>
From:   "Satya Priya Kakitapalli (Temp)" <quic_c_skakit@quicinc.com>
In-Reply-To: <20220727013200.90E37C433C1@smtp.kernel.org>
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On 7/27/2022 7:01 AM, Stephen Boyd wrote:
> Quoting Satya Priya (2022-07-20 04:03:43)
>> From: Taniya Das <quic_tdas@quicinc.com>
>>
>> The clock gating control for TX/RX/WSA core bus clocks would be required
>> to be reset(moved from hardware control) from audio core driver. Thus
>> add the support for the reset clocks.
>>
>> Also add the external mclk to interface external MI2S.
>>
>> Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280").
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> ---
>>   drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++-
>>   drivers/clk/qcom/lpasscorecc-sc7280.c  | 33 +++++++++++++++++++++++++++++++++
>>   2 files changed, 54 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
>> index 6067328..063e036 100644
>> --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
>> +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
>> @@ -23,6 +23,7 @@
>>   #include "clk-regmap-mux.h"
>>   #include "common.h"
>>   #include "gdsc.h"
>> +#include "reset.h"
>>   
>>   enum {
>>          P_BI_TCXO,
>> @@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
>>                  .parent_data = lpass_aon_cc_parent_data_0,
>>                  .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
>>                  .flags = CLK_OPS_PARENT_ENABLE,
>> -               .ops = &clk_rcg2_ops,
>> +               .ops = &clk_rcg2_shared_ops,
> This diff isn't mentioned in the commit text at all. Is it intentional?
> If so, please mention why it needs to change.


It is updated to park the RCG at XO after disable as this clock signal 
is used by hardware to turn ON memories in LPASS. I'll mention this in 
the commit text.