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From:   <Conor.Dooley@microchip.com>
To:     <krzysztof.kozlowski@linaro.org>, <linus.walleij@linaro.org>,
        <brgl@bgdev.pl>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
        <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
        <atulkhare@rivosinc.com>, <sagar.kadam@sifive.com>
CC:     <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 1/2] dt-bindings: sifive: add cache-set value of 2048
Thread-Topic: [PATCH v3 1/2] dt-bindings: sifive: add cache-set value of 2048
Thread-Index: AQHYoRJORxZFGGFwkky2Nc2hNdByz62Q6giAgAABE4CAAOOSAIAAAcEA
Date:   Wed, 27 Jul 2022 07:19:35 +0000
Message-ID: <a530d8c8-7dcb-9cc0-2be3-16567e1a99bc@microchip.com>
References: <20220726170725.3245278-1-mail@conchuod.ie>
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In-Reply-To: <bf470847-9e96-fc5e-0b82-d05068aaeb47@linaro.org>
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