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From:   Biju Das <biju.das.jz@bp.renesas.com>
To:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CC:     Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <anup@brainfault.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK
Thread-Topic: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK
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Date:   Wed, 27 Jul 2022 09:27:56 +0000
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Hi Lad, Prabhakar,

> Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding
> documentation for Renesas RZ/Five SoC and SMARC EVK
>=20
> Hi Krzysztof,
>=20
> Thank you for the review.
>=20
> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> >
> > On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this
> SoC.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > >  .../devicetree/bindings/riscv/renesas.yaml    | 49
> +++++++++++++++++++
> > >  1 file changed, 49 insertions(+)
> > >  create mode 100644
> > > Documentation/devicetree/bindings/riscv/renesas.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > new file mode 100644
> > > index 000000000000..f72f8aea6a82
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
> > > @@ -0,0 +1,49 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:

> > > +
> > > +title: Renesas RZ/Five Platform Device Tree Bindings
> > > +
> > > +maintainers:
> > > +  - Geert Uytterhoeven <geert+renesas@glider.be>
> > > +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > +
> > > +# We want to ignore this schema if the board is SMARC EVK based on
> > > +ARM64 arch
> > > +select:
> > > +  not:
> > > +    properties:
> > > +      compatible:
> > > +        contains:
> > > +          items:
> >
> > I think you should rather ignore the RiscV SoCs, not specific board.
> >
> You mean to ignore ARM/64 SoCs?
>=20
> Agreed just the below enum, should do the trick.
>=20
>             - enum:
>                 - renesas,r9a07g043u11
>                 - renesas,r9a07g043u12
>                 - renesas,r9a07g044c1
>                 - renesas,r9a07g044c2
>                 - renesas,r9a07g044l1
>                 - renesas,r9a07g044l2
>                 - renesas,r9a07g054l1
>                 - renesas,r9a07g054l2

Why do we need to add renesas,r9a07g044 and renesas,r9a07g054
in riscv file? These are arm64 only SoC's.

Cheers,
Biju


>=20
> > > +            - const: renesas,smarc-evk
> > > +            - enum:
> > > +                - renesas,r9a07g043u11
> > > +                - renesas,r9a07g043u12
> > > +                - renesas,r9a07g044c1
> > > +                - renesas,r9a07g044c2
> > > +                - renesas,r9a07g044l1
> > > +                - renesas,r9a07g044l2
> > > +                - renesas,r9a07g054l1
> > > +                - renesas,r9a07g054l2
> > > +            - enum:
> > > +                - renesas,r9a07g043
> > > +                - renesas,r9a07g044
> > > +                - renesas,r9a07g054
> >
> > Did you actually test that it works and properly matches?
> >
> Yes I have run the dtbs_check and dt_binding _check for ARM64 and RISC-
> V. Do you see any cases where it can fail?
>=20
> Cheers,
> Prabhakar