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From:   <Conor.Dooley@microchip.com>
To:     <krzysztof.kozlowski@linaro.org>, <biju.das.jz@bp.renesas.com>,
        <prabhakar.csengg@gmail.com>
CC:     <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        <geert+renesas@glider.be>, <magnus.damm@gmail.com>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
        <aou@eecs.berkeley.edu>, <anup@brainfault.org>,
        <linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK
Thread-Topic: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK
Thread-Index: AQHYoRqa9YiD9Yfw2Eu80dWx4G03OK2R6rmAgAADK4CAAA22gIAAAzUAgAAAzoCAABjHAIAAAfcAgAAKK4CAAARlgIAABXIAgAABLACAAAgYAA==
Date:   Wed, 27 Jul 2022 13:29:11 +0000
Message-ID: <5292fbdd-9eae-2398-1260-cbef652f6af2@microchip.com>
References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
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