Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20220726180623.1668-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <636e9214-4b36-e9a6-3c6b-b6edb944335e@linaro.org> <CA+V-a8sTw1qzuTeD2vb7RgDmmNdEP5qEcxXCjrFgkyrBrLrt5Q@mail.gmail.com>
 <e64cc15e-b31e-876d-b3cf-b60d255c495b@linaro.org> <CA+V-a8u1VW9xaj2KjySyMuegpisLVENO_6uJOpAFZGbKziYLYw@mail.gmail.com>
 <e31e0c1f-4755-704e-8428-93970877d8f5@linaro.org> <CA+V-a8sX=Frs_cds9MriauTFRvcZUNCvoeZ+SaC0GUpL7L6qhg@mail.gmail.com>
 <9f32a4a9-66b4-ba2e-1713-436103c2faf8@linaro.org> <OS0PR01MB5922763582B836DA45CDFF0886979@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <80f08089-e3bb-983e-313b-45613364829e@linaro.org> <OS0PR01MB5922FDF8CFFE44A611D3783886979@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <75e5ace3-3255-2302-65f5-9fbef9cb1147@linaro.org> <5292fbdd-9eae-2398-1260-cbef652f6af2@microchip.com>
In-Reply-To: <5292fbdd-9eae-2398-1260-cbef652f6af2@microchip.com>
From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 27 Jul 2022 16:32:28 +0100
Message-ID: <CA+V-a8vVOXeqUZL7fTVHrc1qnC==uLR+nHooz=1mg-K3BwW3mQ@mail.gmail.com>
Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for
 Renesas RZ/Five SoC and SMARC EVK
To:     Conor.Dooley@microchip.com
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Biju Das <biju.das.jz@bp.renesas.com>,
        "Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <anup@brainfault.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Wed, Jul 27, 2022 at 2:29 PM <Conor.Dooley@microchip.com> wrote:
>
> On 27/07/2022 14:00, Krzysztof Kozlowski wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 27/07/2022 14:56, Biju Das wrote:
> >>>
> >>> Then it is not the same SoC! Same means same, identical. CPU
> >>> architecture is one of the major differences, which means it is not the
> >>> same.
> >>
> >> Family SoC(R9A07G043) is at top level. Then it has different SoCId for taking care of
> >> differences for SoC based on ARMV8 and RISC-V which has separate compatible like
> >> r9a07g043u11 and r9a07g043f01?
> >
> > This does not answer the concern - it's not the same SoC. The most
> > generic compatible denotes the most common part. I would argue that
> > instruction set and architecture are the most important differences.
> > None of ARMv8 SoCs (SoCs, not CPU cores) have "arm,armv8" compatible and
> > you went even more - you combined two architectures in the most generic
> > compatibles.
>
> I would have to agree with this. The most "core" part of the SoC is
> its architecture and while the peripheral IPs might be the same etc
> & the Renesas marketing team might have put them in the same "family",
> for the purposes of a device tree I don't see how having a common
> fallback makes sense.
>
Agreed, I was following the same which we have done on the ARM64 schema.

I am waiting on Geert's feedback on whether we should follow as
Krzysztof suggested ie to have

renesas,smarc-evk-r9a07g043f01 - for the board
renesas,9a07g043f01 - for the SoC

Cheers,
Prabhakar