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[78.26.46.173]) by smtp.gmail.com with ESMTPSA id l13-20020a19c20d000000b00489c6c76385sm97465lfc.268.2022.07.28.02.02.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jul 2022 02:02:29 -0700 (PDT) Message-ID: <367cf98b-ef06-8f44-76c8-9099a1ec13dc@linaro.org> Date: Thu, 28 Jul 2022 11:02:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH V2 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Content-Language: en-US To: Jerome Brunet , Yu Tu , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl References: <20220728054202.6981-1-yu.tu@amlogic.com> <20220728054202.6981-2-yu.tu@amlogic.com> <82e3fd36-df96-a555-4cea-47fabd26502b@linaro.org> <1jv8rhfw8h.fsf@starbuckisacylon.baylibre.com> From: Krzysztof Kozlowski In-Reply-To: <1jv8rhfw8h.fsf@starbuckisacylon.baylibre.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28/07/2022 10:50, Jerome Brunet wrote: > > On Thu 28 Jul 2022 at 10:41, Krzysztof Kozlowski wrote: > >> On 28/07/2022 07:42, Yu Tu wrote: >>> Add new clock controller compatible and dt-bindings header for the >>> Everything-Else domain of the S4 SoC. >>> >>> Signed-off-by: Yu Tu >> >> >> >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index c1abc53f9e91..f872d0c0c253 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic* >>> F: drivers/clk/meson/ >>> F: include/dt-bindings/clock/gxbb* >>> F: include/dt-bindings/clock/meson* >>> +F: include/dt-bindings/clock/s4-clkc.h >>> >>> ARM/Amlogic Meson SoC Crypto Drivers >>> M: Corentin Labbe >>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h >>> new file mode 100644 >>> index 000000000000..b686c8877419 >>> --- /dev/null >>> +++ b/include/dt-bindings/clock/s4-clkc.h >> >> Filename with vendor prefix, so: >> amlogic,s4-clkc.h >> >>> @@ -0,0 +1,146 @@ >>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ >>> +/* >>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. >>> + * Author: Yu Tu >>> + */ >>> + >>> +#ifndef _DT_BINDINGS_CLOCK_S4_CLKC_H >>> +#define _DT_BINDINGS_CLOCK_S4_CLKC_H >>> + >>> +/* >>> + * CLKID index values >>> + */ >>> + >>> +#define CLKID_FIXED_PLL 1 >>> +#define CLKID_FCLK_DIV2 3 >>> +#define CLKID_FCLK_DIV3 5 >>> +#define CLKID_FCLK_DIV4 7 >>> +#define CLKID_FCLK_DIV5 9 >>> +#define CLKID_FCLK_DIV7 11 >> >> Why these aren't continuous? IDs are expected to be incremented by 1. >> > > All clocks have IDs, it is one big table in the driver, but we are not exposing them all. > For example, with composite 'mux / div / gate' assembly, we usually need > only the leaf. I understand you do not expose them all, but that is not the reason to increment ID by 2 or 3... Otherwise these are not IDs and you are not expected to put register offsets into the bindings (you do not bindings in such case). > Same has been done for the other AML controllers: > For ex: > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/gxbb-clkc.h This cannot be fixed now, but it is very poor argument. Like saying "we had a bug in other driver, so we implemented the bug here as well". Best regards, Krzysztof