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Hou" , Biwen Li , Sean Anderson Subject: Re: [PATCH v3] irqchip/ls-extirq: fix invalid wait context by avoiding to use regmap Thread-Topic: [PATCH v3] irqchip/ls-extirq: fix invalid wait context by avoiding to use regmap Thread-Index: AQHYodNDgTwSkPcX40WBBOsOXPckLq2TaDgAgABgqQA= Date: Thu, 28 Jul 2022 13:30:57 +0000 Message-ID: <20220728133056.3lsrlxkc2lhtwhih@skbuf> References: <20220727160915.3648155-1-vladimir.oltean@nxp.com> <87zggtwuit.wl-maz@kernel.org> In-Reply-To: <87zggtwuit.wl-maz@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 873c7740-34ba-4f73-9aef-08da709d674c x-ms-traffictypediagnostic: AM5PR0401MB2449:EE_ x-ld-processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 873c7740-34ba-4f73-9aef-08da709d674c X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jul 2022 13:30:57.1127 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: avI1bVPqsygVJvyTJID9Q6aYQgE3HgPQXEWB+nPCq5KqaNqq1fh1tc3kJAdlzGtn74uK+VrUfQ9mVi6wfi0/4A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0401MB2449 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Marc, On Thu, Jul 28, 2022 at 08:44:58AM +0100, Marc Zyngier wrote: > On Wed, 27 Jul 2022 17:09:15 +0100, > Vladimir Oltean wrote: > >=20 > > The irqchip->irq_set_type method is called by __irq_set_trigger() under > > the desc->lock raw spinlock. > >=20 > > The ls-extirq implementation, ls_extirq_irq_set_type(), uses an MMIO > > regmap created by of_syscon_register(), which uses plain spinlocks > > (the kind that are sleepable on RT). > >=20 > > Therefore, this is an invalid locking scheme for which we get a kernel > > splat stating just that ("[ BUG: Invalid wait context ]"), because the > > context in which the plain spinlock may sleep is atomic due to the raw > > spinlock. We need to go raw spinlocks all the way. >=20 > Interesting you say that... > > - regmap_update_bits(priv->syscon, priv->intpcr, mask, value); > > + > > + intpcr =3D priv->read(priv->intpcr); > > + intpcr &=3D ~mask; > > + intpcr |=3D value; > > + priv->write(priv->intpcr, intpcr); >=20 > Which really begs a few questions: >=20 > - Where is the locking gone? Sure, the warning is gone. But the driver > is now broken for *all* configurations, and not only RT. Result! Correct, I had assumed that calls to irq_chip :: irq_set_type() are implicitly serialized with respect to each other by means of the irq descriptor's desc->lock, but clearly that is only true for a single interrupt line. So I'll add back a lock that keeps the rmw atomic. > - Is it *really* worth it to have 4 dumb helpers that bring nothing in > terms of abstraction, and two indirections for something that could > equally be expressed with a conditional? Probably not, but it was a choice no worse than going through regmap's own indirection. I'll try to come up with something that avoids function pointers.=