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Message-ID: <c297fc36-5d0e-6c89-af4a-0d63977811c4@intel.com>
Date:   Fri, 29 Jul 2022 11:49:40 +0300
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Subject: Re: [PATCH V1 1/1] mmc:sdhci-pci-o2micro:fix some SD cards
 compatibility issue at ddr50 mode
Content-Language: en-US
To:     Chevron Li <chevron.li@bayhubtech.com>, ulf.hansson@linaro.org,
        linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc:     shaper.liu@bayhubtech.com, shirley.her@bayhubtech.com,
        xiaoguang.yu@bayhubtech.com
References: <20220727033123.304-1-chevron.li@bayhubtech.com>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
In-Reply-To: <20220727033123.304-1-chevron.li@bayhubtech.com>
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On 27/07/22 06:31, Chevron Li wrote:
> Bayhub chips have better compatibility support for sdr50 than ddr50

Upper case would be better for SDR50 and DDR50

> and both mode have the same R/W performance.

Only if the max frequency is 100 MHz.  Is that always the case?

Perhaps comment on that in the commit message.

> Disable ddr50 mode and use sdr50 instead.

Upper case would be better for SDR50 and DDR50

> 
> Signed-off-by: Chevron Li<chevron.li@bayhubtech.com>

For neatness, a space before "<" above would be better, and
also a space after ":" in the subject

> ---
> Changes on V1:
> 1.Set quirks2 flag SDHCI_QUIRK2_BROKEN_DDR50 for bayhub chips.
> 2.Use bayhub hardware input tuning for SDR50 mode instead of standard tuning flow.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 0d4d343dbb77..ad457cd9cbaa 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -317,11 +317,12 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>  	u32 reg_val;
>  
>  	/*
> -	 * This handler only implements the eMMC tuning that is specific to
> +	 * This handler implements the hardware tuning that is specific to
>  	 * this controller.  Fall back to the standard method for other TIMING.
>  	 */
>  	if ((host->timing != MMC_TIMING_MMC_HS200) &&
> -		(host->timing != MMC_TIMING_UHS_SDR104))
> +		(host->timing != MMC_TIMING_UHS_SDR104) &&
> +		(host->timing != MMC_TIMING_UHS_SDR50))
>  		return sdhci_execute_tuning(mmc, opcode);
>  
>  	if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
> @@ -631,6 +632,8 @@ static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
>  		if (reg & 0x1)
>  			host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
>  
> +		host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
> +
>  		sdhci_pci_o2_enable_msi(chip, host);
>  
>  		if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
> 
> base-commit: 68e77ffbfd06ae3ef8f2abf1c3b971383c866983