Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Fri, 29 Jul 2022 22:57:57 +0800
From:   Xu Yilun <yilun.xu@intel.com>
To:     Daniel =?iso-8859-1?Q?Gl=F6ckner?= <dg@emlix.com>
Cc:     Ivan Bornyakov <i.bornyakov@metrotek.ru>, mdf@kernel.org,
        hao.wu@intel.com, trix@redhat.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        system@metrotek.ru,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v5 2/2] dt-bindings: fpga: add binding doc for ecp5-spi
  fpga mgr
Message-ID: <20220729145757.GA2601292@yilunxu-OptiPlex-7050>
References: <20220719112335.9528-1-i.bornyakov@metrotek.ru>
 <20220719112335.9528-3-i.bornyakov@metrotek.ru>
 <20220729090123.GA28299@homes.emlix.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <20220729090123.GA28299@homes.emlix.com>
Precedence: bulk

On Fri, Jul 29, 2022 at 11:01:24AM +0200, Daniel Gl?ckner wrote:
> Hi,
> 
> On Tue, Jul 19, 2022 at 02:23:35PM +0300, Ivan Bornyakov wrote:
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - lattice,ecp5-fpga-mgr
> 
> Since this driver uses the same interface as the existing
> drivers/fpga/machxo2-spi.c driver, wouldn't it be advisable to use a
> similar compatible id, i.e. lattice,ecp5-slave-spi?

That's a good clue for me. I searched the machxo2 & ecp5 Programming
Usage Guide and seems they share the similar slave SPI sysCONFIG
interface, at least the command word tables are the same. So could we
have a generic driver for the lattice slave SPI sysCONFIG interface,
rather than create similar drivers for each board?

Thanks,
Yilun

> 
> > +required:
> > +  - compatible
> > +  - reg
> > +  - program-gpios
> > +  - init-gpios
> > +  - done-gpios
> 
> I think some of the GPIOs can be made optional by reading the status
> register or using the refresh command, assuming the slave spi interface
> stayed enabled after previous programming and we are not dealing with
> several chained FPGAs. But that can of course be left as an exercise for
> other developers.
> 
> Best regards,
> 
>   Daniel