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Date:   Mon, 1 Aug 2022 12:12:47 -0400 (EDT)
From:   Mikulas Patocka <mpatocka@redhat.com>
To:     Will Deacon <will@kernel.org>
cc:     Linus Torvalds <torvalds@linux-foundation.org>,
        "Paul E. McKenney" <paulmck@kernel.org>,
        Ard Biesheuvel <ardb@kernel.org>,
        Alexander Viro <viro@zeniv.linux.org.uk>,
        Alan Stern <stern@rowland.harvard.edu>,
        Andrea Parri <parri.andrea@gmail.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Boqun Feng <boqun.feng@gmail.com>,
        Nicholas Piggin <npiggin@gmail.com>,
        David Howells <dhowells@redhat.com>,
        Jade Alglave <j.alglave@ucl.ac.uk>,
        Luc Maranget <luc.maranget@inria.fr>,
        Akira Yokosawa <akiyks@gmail.com>,
        Daniel Lustig <dlustig@nvidia.com>,
        Joel Fernandes <joel@joelfernandes.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-arch <linux-arch@vger.kernel.org>,
        linux-fsdevel@vger.kernel.org
Subject: Re: [PATCH v4 1/2] introduce test_bit_acquire and use it in
 wait_on_bit
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On Mon, 1 Aug 2022, Will Deacon wrote:

> On Mon, Aug 01, 2022 at 06:42:15AM -0400, Mikulas Patocka wrote:
> 
> > Index: linux-2.6/arch/x86/include/asm/bitops.h
> > ===================================================================
> > --- linux-2.6.orig/arch/x86/include/asm/bitops.h	2022-08-01 12:27:43.000000000 +0200
> > +++ linux-2.6/arch/x86/include/asm/bitops.h	2022-08-01 12:27:43.000000000 +0200
> > @@ -203,8 +203,10 @@ arch_test_and_change_bit(long nr, volati
> >  
> >  static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
> >  {
> > -	return ((1UL << (nr & (BITS_PER_LONG-1))) &
> > +	bool r = ((1UL << (nr & (BITS_PER_LONG-1))) &
> >  		(addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
> > +	barrier();
> > +	return r;
> 
> Hmm, I find it a bit weird to have a barrier() here given that 'addr' is
> volatile and we don't need a barrier() like this in the definition of
> READ_ONCE(), for example.

gcc doesn't reorder two volatile accesses, but it can reorder non-volatile
accesses around volatile accesses.

The purpose of the compiler barrier is to make sure that the non-volatile 
accesses that follow test_bit are not reordered by the compiler before the 
volatile access to addr.

> > Index: linux-2.6/include/linux/wait_bit.h
> > ===================================================================
> > --- linux-2.6.orig/include/linux/wait_bit.h	2022-08-01 12:27:43.000000000 +0200
> > +++ linux-2.6/include/linux/wait_bit.h	2022-08-01 12:27:43.000000000 +0200
> > @@ -71,7 +71,7 @@ static inline int
> >  wait_on_bit(unsigned long *word, int bit, unsigned mode)
> >  {
> >  	might_sleep();
> > -	if (!test_bit(bit, word))
> > +	if (!test_bit_acquire(bit, word))
> >  		return 0;
> >  	return out_of_line_wait_on_bit(word, bit,
> >  				       bit_wait,
> 
> Yet another approach here would be to leave test_bit as-is and add a call to
> smp_acquire__after_ctrl_dep() since that exists already -- I don't have
> strong opinions about it, but it saves you having to add another stub to
> x86.

It would be the same as my previous patch with smp_rmb() that Linus didn't 
like. But I think smp_rmb (or smp_acquire__after_ctrl_dep) would be 
correct here.

> Will

Mikulas