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Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second
 VPE
From:   Sander Vanheule <sander@svanheule.net>
To:     Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc:     Marc Zyngier <maz@kernel.org>,
        Aleksander Jan Bajkowski <olek2@wp.pl>,
        Hauke Mehrtens <hauke@hauke-m.de>, git@birger-koblitz.de,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Date:   Mon, 01 Aug 2022 18:02:38 +0200
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Hi Thomas,

On Mon, 2022-08-01 at 17:25 +0200, Thomas Bogendoerfer wrote:
> On Thu, Jul 28, 2022 at 05:50:10PM +0200, Martin Blumenstingl wrote:
> > I think for the Realtek SoC's this would be problematic because it's
> > using MIPS_GENERIC. My understanding is that in an ideal world all
>=20
> which SOC are these ?

That would be the SoCs supported by MACH_REALTEK_RTL. More specifically, th=
e
ones affected by this issue are the RTL8391M, RTL8392M, RTL8393M, and RTL83=
96M
which have two VPEs.

The SoC interrupt controller on these chips can route interrupts to all CPU=
 HW
interrupts. If only IP6 and IP7 are enabled on the second VPE, anything rou=
ted
there to IP2-IP5 ends up in a black hole.

Best,
Sander

>=20
> > platforms would switch to MIPS_GENERIC.
> > As an alternative to making irq-mips-cpu capable of changing another
> > CPU's registers: would you also be happy with a change that implements
> > the following idea (pseudocode) in vsmp_init_secondary():
> > =C2=A0=C2=A0=C2=A0 struct device_node *root_node =3D of_find_node_by_pa=
th("/");
> >=20
> > =C2=A0=C2=A0=C2=A0 if (mips_gic_present() ||
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 of_device_is_compatible(root=
_node, "lantiq,xrx200") ||
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 of_device_is_compatible(root=
_node, "realtek,some-relevant-soc"))
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 change_c0_status(ST0_IM, STA=
TUSF_IP2 | STATUSF_IP3 |
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 STAT=
USF_IP4 | STATUSF_IP5 |
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 STAT=
USF_IP6 | STATUSF_IP7);
> > =C2=A0=C2=A0=C2=A0 else
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ...
> >=20
> > =C2=A0=C2=A0=C2=A0 of_node_put(root_node);
> >=20
> > That way we don't risk enabling interrupt lines which shouldn't be
> > enabled (on SoCs which we don't know).
> > And also it would not cause any issues with MIPS_GENERIC support.
>=20
> well it's not exactly the abstraction I'm looking for, but it's ok for me
> as a short term way to move forward.
>=20
> Thomas.
>=20