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Message-ID: <b92ef74c-1068-b86e-c3c2-a95f057e2494@acm.org>
Date:   Mon, 1 Aug 2022 10:34:51 -0700
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Subject: Re: [PATCH v1] scsi: ufs: Fix ufshcd_scale_clks decision in recovery
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To:     Stanley Chu <chu.stanley@gmail.com>
Cc:     Stanley Chu <stanley.chu@mediatek.com>, linux-scsi@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        "Martin K . Petersen" <martin.petersen@oracle.com>,
        Avri Altman <avri.altman@wdc.com>, alim.akhtar@samsung.com,
        "James E.J. Bottomley" <jejb@linux.ibm.com>,
        peter.wang@mediatek.com, Chun-Hung Wu <chun-hung.wu@mediatek.com>,
        alice.chao@mediatek.com, powen.kao@mediatek.com,
        mason.zhang@mediatek.com, qilin.tan@mediatek.com,
        lin.gui@mediatek.com, eddie.huang@mediatek.com,
        tun-yu.yu@mediatek.com, cc.chou@mediatek.com,
        chaotian.jing@mediatek.com, jiajie.hao@mediatek.com
References: <20220729075519.4665-1-stanley.chu@mediatek.com>
 <7e8c58cf-64c1-8426-bf22-97d3df85ed38@acm.org>
 <CAGaU9a_G1kH8VezozhZ3-S6-GvMr=EUVc4btU8Dwdo+cCJDxUg@mail.gmail.com>
From:   Bart Van Assche <bvanassche@acm.org>
In-Reply-To: <CAGaU9a_G1kH8VezozhZ3-S6-GvMr=EUVc4btU8Dwdo+cCJDxUg@mail.gmail.com>
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On 7/30/22 00:08, Stanley Chu wrote:
> Hi Bart,
> 
> On Sat, Jul 30, 2022 at 4:12 AM Bart Van Assche <bvanassche@acm.org> wrote:
>>
>> On 7/29/22 00:55, Stanley Chu wrote:
>>> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
>>> index 581d88af07ab..dc57a7988023 100644
>>> --- a/drivers/ufs/core/ufshcd.c
>>> +++ b/drivers/ufs/core/ufshcd.c
>>> @@ -1574,8 +1574,6 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
>>>        ufshcd_rpm_get_sync(hba);
>>>        ufshcd_hold(hba, false);
>>>
>>> -     hba->clk_scaling.is_enabled = value;
>>> -
>>>        if (value) {
>>>                ufshcd_resume_clkscaling(hba);
>>>        } else {
>>> @@ -1586,6 +1584,8 @@ static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
>>>                                        __func__, err);
>>>        }
>>>
>>> +     hba->clk_scaling.is_enabled = value;
>>> +
>>>        ufshcd_release(hba);
>>>        ufshcd_rpm_put_sync(hba);
>>>    out:
>>> @@ -7259,7 +7259,8 @@ static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
>>>        hba->silence_err_logs = false;
>>>
>>>        /* scale up clocks to max frequency before full reinitialization */
>>> -     ufshcd_scale_clks(hba, true);
>>> +     if (ufshcd_is_clkscaling_supported(hba) && hba->clk_scaling.is_enabled)
>>> +             ufshcd_scale_clks(hba, true);
>>>
>>>        err = ufshcd_hba_enable(hba);
>>
>> I see a race condition between the hba->clk_scaling.is_enabled check in
>> ufshcd_host_reset_and_restore() and the code that sets
>> ufshcd_clkscale_enable_store(). Shouldn't the code in
>> ufshcd_host_reset_and_restore() that scales up the clocks be serialized
>> against ufshcd_clkscale_enable_store()?
> 
> Both check and set paths are serialized by hba->host_sem currently.
> 
> Would I miss any other unserialized paths?

Where in ufshcd_host_reset_and_restore() or in its callers is 
hba->host_sem obtained? I don't see it. Am I perhaps overlooking something?

Thanks,

Bart.