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From:   David Laight <David.Laight@ACULAB.COM>
To:     'Boqun Feng' <boqun.feng@gmail.com>,
        Mikulas Patocka <mpatocka@redhat.com>
CC:     Will Deacon <will@kernel.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        "Paul E. McKenney" <paulmck@kernel.org>,
        "Ard Biesheuvel" <ardb@kernel.org>,
        Alexander Viro <viro@zeniv.linux.org.uk>,
        "Alan Stern" <stern@rowland.harvard.edu>,
        Andrea Parri <parri.andrea@gmail.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Nicholas Piggin <npiggin@gmail.com>,
        David Howells <dhowells@redhat.com>,
        Jade Alglave <j.alglave@ucl.ac.uk>,
        "Luc Maranget" <luc.maranget@inria.fr>,
        Akira Yokosawa <akiyks@gmail.com>,
        "Daniel Lustig" <dlustig@nvidia.com>,
        Joel Fernandes <joel@joelfernandes.org>,
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        linux-arch <linux-arch@vger.kernel.org>,
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Subject: RE: [PATCH v4 1/2] introduce test_bit_acquire and use it in
 wait_on_bit
Thread-Topic: [PATCH v4 1/2] introduce test_bit_acquire and use it in
 wait_on_bit
Thread-Index: AQHYpdMdL3R9dRhMTUG852+RirbLDa2bPhCA
Date:   Tue, 2 Aug 2022 08:00:48 +0000
Message-ID: <31eb3681cfcf4b238a12a82c175457bc@AcuMS.aculab.com>
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From: Boqun Feng
> Sent: 01 August 2022 19:17
> 
> On Mon, Aug 01, 2022 at 12:12:47PM -0400, Mikulas Patocka wrote:
> >
> >
> > On Mon, 1 Aug 2022, Will Deacon wrote:
> >
> > > On Mon, Aug 01, 2022 at 06:42:15AM -0400, Mikulas Patocka wrote:
> > >
> > > > Index: linux-2.6/arch/x86/include/asm/bitops.h
> > > > ===================================================================
> > > > --- linux-2.6.orig/arch/x86/include/asm/bitops.h	2022-08-01 12:27:43.000000000 +0200
> > > > +++ linux-2.6/arch/x86/include/asm/bitops.h	2022-08-01 12:27:43.000000000 +0200
> > > > @@ -203,8 +203,10 @@ arch_test_and_change_bit(long nr, volati
> > > >
> > > >  static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
> > > >  {
> > > > -	return ((1UL << (nr & (BITS_PER_LONG-1))) &
> > > > +	bool r = ((1UL << (nr & (BITS_PER_LONG-1))) &
> > > >  		(addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
> > > > +	barrier();
> > > > +	return r;
> > >
> > > Hmm, I find it a bit weird to have a barrier() here given that 'addr' is
> > > volatile and we don't need a barrier() like this in the definition of
> > > READ_ONCE(), for example.
> >
> > gcc doesn't reorder two volatile accesses, but it can reorder non-volatile
> > accesses around volatile accesses.
> >
> > The purpose of the compiler barrier is to make sure that the non-volatile
> > accesses that follow test_bit are not reordered by the compiler before the
> > volatile access to addr.
> >
> 
> Better to have a constant_test_bit_acquire()? I don't think all
> test_bit() call sites need the ordering?

It is also unlikely that the compiler will 'usefully' move a read
across the test_bit() call - which is likely to be in a conditional.
So barrier() is unlikely to significantly affect the generated code.

Indeed, perhaps test_bit() should always enforce read ordering
even one weakly ordered cpu?
It is used with set_bit() and clear_bit() which are expensive
locked operations - so a slightly more expensive test_bit()
probably doesn't matter.

Remember these aren't functions to replace &= and |=.
(In spite of some code paths.)

	David

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