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Date:   Wed, 3 Aug 2022 17:37:43 -0600
From:   Rob Herring <robh@kernel.org>
To:     Liu Ying <victor.liu@nxp.com>
Cc:     devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org,
        shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de,
        festevam@gmail.com, linux-imx@nxp.com, saravanak@google.com,
        gregkh@linuxfoundation.org, geert+renesas@glider.be,
        krzysztof.kozlowski@linaro.org
Subject: Re: [PATCH v2 3/3] dt-bindings: bus: Add Freescale i.MX8qxp pixel
 link MSI bus binding
Message-ID: <20220803233743.GA2813240-robh@kernel.org>
References: <20220803012421.3410226-1-victor.liu@nxp.com>
 <20220803012421.3410226-4-victor.liu@nxp.com>
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On Wed, Aug 03, 2022 at 09:24:21AM +0800, Liu Ying wrote:
> Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus.
> It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI
> DSI and HDMI TX subsystems, like I2C controller, PWM controller,
> MIPI DSI controller and Control and Status Registers (CSR) module.
> 
> Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel
> link MSI bus specific bindings.
> 
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> v1->v2:
> Address Krzysztof's comments:
> * Add a select to explicitly select the MSI bus dt-binding.
> * List 'simple-pm-bus' explicitly as one item of compatible strings.
> * Require compatible and reg properties.
> * Put reg property just after compatible property in example.
> 
>  .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml   | 97 +++++++++++++++++++
>  1 file changed, 97 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
> 
> diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
> new file mode 100644
> index 000000000000..358c032041e5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
> +
> +maintainers:
> +  - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> +  i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
> +  sitting together with the PHYs.  It is not the same as the MSI bus coming
> +  from i.MX8 System Controller Unit (SCU) which is used to control power,
> +  clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
> +
> +  i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
> +  that is, MSI clock and AHB clock, need to be enabled so that peripherals
> +  connected to the bus can be accessed. Also, the bus is part of a power
> +  domain. The power domain needs to be enabled before the peripherals can
> +  be accessed.
> +
> +  Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
> +  like I2C controller, PWM controller, MIPI DSI controller and Control and
> +  Status Registers (CSR) module, are accessed through the bus.
> +
> +  The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
> +  pixel link MSI bus controller and does not allow SCFW user to control it.
> +  So, the controller's registers cannot be accessed by SCFW user. Hence,
> +  the interrupts generated by the controller don't make any sense from SCFW
> +  user's point of view.
> +
> +allOf:
> +  - $ref: simple-pm-bus.yaml#
> +
> +# We need a select here so we don't match all nodes with 'simple-pm-bus'.
> +select:
> +  properties:
> +    compatible:
> +      contains:
> +        enum:
> +          - fsl,imx8qxp-display-pixel-link-msi-bus
> +          - fsl,imx8qm-display-pixel-link-msi-bus
> +  required:
> +    - compatible
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - fsl,imx8qxp-display-pixel-link-msi-bus
> +          - fsl,imx8qm-display-pixel-link-msi-bus
> +      - const: simple-pm-bus
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: master gated clock from system
> +      - description: AHB clock
> +
> +  clock-names:
> +    items:
> +      - const: msi
> +      - const: ahb
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - power-domains
> +
> +unevaluatedProperties: false

No child nodes allowed?

> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/imx8-lpcg.h>
> +    #include <dt-bindings/firmware/imx/rsrc.h>
> +    bus@56200000 {
> +        compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
> +        reg = <0x56200000 0x20000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        interrupt-parent = <&dc0_irqsteer>;
> +        interrupts = <320>;
> +        ranges;
> +        clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>,
> +                 <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>;
> +        clock-names = "msi", "ahb";
> +        power-domains = <&pd IMX_SC_R_DC_0>;
> +    };
> -- 
> 2.25.1
> 
>