Received: by 2002:ac0:e350:0:0:0:0:0 with SMTP id g16csp282313imn; Thu, 4 Aug 2022 05:58:38 -0700 (PDT) X-Google-Smtp-Source: AA6agR5xC5JBDiGF6Kc8T53CWkUuMhAZwFO+Ad5+4bodGEsufBGLvAqYW4fxx5Zxs+/adQEq2uKg X-Received: by 2002:a65:6c05:0:b0:41a:d13f:f0fb with SMTP id y5-20020a656c05000000b0041ad13ff0fbmr1556261pgu.393.1659617917828; Thu, 04 Aug 2022 05:58:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1659617917; cv=none; d=google.com; s=arc-20160816; b=BB1TcgPG2EcZDizHNsvK0hs58mbWs9cGfiJgGjCvuCt8bg/89PtoTZOPT/XxCE8ZeA dmMM5SGyhF0K4gJhHQ3L92LNjjBzpW953ZNOTlI6JF5Sg7ebFIx3iwa7fNniN3+btGcd 0/eTOp/PcpHkAktClPt29iZwTAIu+ey3j2K0ukg1eVHe66s61mjjlU0dy5JEkRDgjacY M0rSezbgFFy2YTmef1wtnEFeglnJcpbx6N38PTn/pDqnuSnE2bG1rzRLcEhDbNOfh+Rx lLWF0XTKX9Z7YeXidWlKCKQreevb6aKTbwBWb9Dm1iv82FQaFBoWTTm/WqZ/69nPislh g4MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=eYJKfAmQK1XYoPxIBrFPmNLPdCFmguzeuw6G21SPhAk=; b=0VOchRsHtgtCVrI48FKsVnRsLh4JzYOS/4x3kQLL6ACCkaQrwWtm6uDFNMj8jj/edX icWBzNZY30nsBXWGWlltFQJ8BTbNfWzYVDSFRuSmLy8J2XXYWRrxXXJ3JcU9KtqU9py6 G26hLSz/HFJKQi5HcKzjhfzOJqyHv3EIUgegw0uIebdZphEEpHdIp8/YvdIElJKwgHmG vCXjAyp+bujzstVpTJZIuqSwET+cHIohIvidyeny/FH2YBSMTsHAi8HAIEFJSR9u7uP/ QAJAW7QhLp0qsuynvTxv1PZFE1z+iDZxky3Mritnu4G0WwuJYW12SzFFdrmsSoKQFBFC gLHw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s6-20020a056a00194600b0052ac8eee909si994226pfk.300.2022.08.04.05.58.22; Thu, 04 Aug 2022 05:58:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239746AbiHDMwN (ORCPT + 99 others); Thu, 4 Aug 2022 08:52:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230140AbiHDMwK (ORCPT ); Thu, 4 Aug 2022 08:52:10 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3A2B1D0F6 for ; Thu, 4 Aug 2022 05:52:09 -0700 (PDT) Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1oJaKR-0002aq-P0; Thu, 04 Aug 2022 14:51:55 +0200 Received: from mfe by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1oJaKP-0001In-0S; Thu, 04 Aug 2022 14:51:53 +0200 Date: Thu, 4 Aug 2022 14:51:52 +0200 From: Marco Felsch To: Dave Stevenson Cc: Adam Ford , Neil Armstrong , David Airlie , dri-devel , Laurent Pinchart , Andrzej Hajda , Marek Szyprowski , Marek Vasut , Jernej Skrabec , Jagan Teki , robert.chiras@nxp.com, laurentiu.palcu@nxp.com, NXP Linux Team , Jonas Karlman , Sascha Hauer , arm-soc , Linux Kernel Mailing List , Robert Foss , Pengutronix Kernel Team , Shawn Guo Subject: Re: imx8mm lcdif->dsi->adv7535 no video, no errors Message-ID: <20220804125152.idyzetjqkjzgbbm2@pengutronix.de> References: <20220802080820.jyf3tfpgcj3pvbtp@pengutronix.de> <20220803062024.vn7awasmifkp5xow@pengutronix.de> <20220804093829.42kdelp7u4r743nv@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Dave, On 22-08-04, Dave Stevenson wrote: > Hi Marco > > On Thu, 4 Aug 2022 at 10:38, Marco Felsch wrote: > > > > Hi Dave, Adam, > > > > On 22-08-03, Dave Stevenson wrote: > > > Hi Adam > > > > > > On Wed, 3 Aug 2022 at 12:03, Adam Ford wrote: > > > > ... > > > > > > > Did managed to get access to the ADV7535 programming guide? This is the > > > > > black box here. Let me check if I can provide you a link with our repo > > > > > so you can test our current DSIM state if you want. > > > > > > > > I do have access to the programming guide, but it's under NDA, but > > > > I'll try to answer questions if I can. > > > > > > Not meaning to butt in, but I have datasheets for ADV7533 and 7535 > > > from previously looking at these chips. > > > > Thanks for stepping into :) > > > > > Mine fairly plainly states: > > > "The DSI receiver input supports DSI video mode operation only, and > > > specifically, only supports nonburst mode with sync pulses". > > > > I've read this also, and we are working in nonburst mode with sync > > pulses. I have no access to an MIPI-DSI analyzer therefore I can't > > verify it. > > > > > Non-burst mode meaning that the DSI pixel rate MUST be the same as the > > > HDMI pixel rate. > > > > On DSI side you don't have a pixel-clock instead there is bit-clock. > > You have an effective pixel clock, with a fixed conversion for the > configuration. > > DSI bit-clock * number of lanes / bits_per_pixel = pixel rate. > 891Mbit/s * 4 lanes / 24bpp = 148.5 Mpixels/s Okay, I just checked the bandwidth which must equal. > As noted elsewhere, the DSI is DDR, so the clock lane itself is only > running at 891 / 2 = 445.5MHz. > > > > Section 6.1.1 "DSI Input Modes" of adv7533_hardware_user_s_guide is > > > even more explicit about the requirement of DSI timing matching > > > > Is it possible to share the key points of the requirements? > > "Specifically the ADV7533 supports the Non-Burst Mode with syncs. This > mode requires real time data generation as a pulse packet received > becomes a pulse generated. Therefore this mode requires a continuous > stream of data with correct video timing to avoid any visual > artifacts." > > LP mode is supported on data lanes. Clock lane must remain in HS mode. > > "... the goal is to accurately convey DPI-type timing over DSI. This > includes matching DPI pixel-transmission rates, and widths of timing > events." Thanks for sharing. > > > The NXP kernel switching down to an hs_clk of 445.5MHz would therefore > > > be correct for 720p operation. > > > > It should be absolute no difference if you work on 891MHz with 2 lanes > > or on 445.5 MHz with 4 lanes. What must be ensured is that you need the > > minimum required bandwidth which is roughly: 1280*720*24*60 = 1.327 > > GBps. > > Has someone changed the number of lanes in use? I'd missed that if so, > but I'll agree that 891MHz over 2 lanes should work for 720p60. The ADV driver is changing it autom. but this logic is somehow odd and there was already a approach to stop the driver doing this. To sync up: we have two problems: 1) The 720P mode with static DSI host configuration isn't working without hacks. 2) The DSI link frequency should changed as soon as required automatically. So we can provide all modes. I would concentrate on problem 1 first before moving on to the 2nd. > I have just noted that 720p59.94 at 24bpp on 4 lanes is listed as one > of the modes that is mandatory to use the timing generator (reg 0x27 > bit 7 = 1). On 2 lanes it is not required. > I don't know why it's referencing the 1000/1001 pixel clock rates and > not the base one, as it's only a base clock change with the same > timing (74.176MHz clock instead of 74.25MHz). Interesting! I would like to know how the HDMI block gets fetched by the DSI block and how the timing-generator can influence this in good/bad way. So that we know what DSI settings (freq, lanes) are sufficient. > > > If you do program the manual DSI divider register to allow a DSI pixel > > > rate of 148.5MHz vs HDMI pixel rate of 74.25MHz, you'd be relying on > > > > There is no such DSI pixel rate to be precise, we only have a DSI bit > > clock/rate. > > > > > the ADV753x having at least a half-line FIFO between DSI rx and HDMI > > > tx to compensate for the differing data rates. I see no reference to > > > such, and I'd be surprised if it was more than a half dozen pixels to > > > compensate for the jitter in the cases where the internal timing > > > generator is mandatory due to fractional bytes. > > > > This is interesting and would proofs our assumption that the device > > don't have a FIFO :) > > > > Our assumptions (we don't have the datasheet/programming manual): > > - HDMI part is fetching 3 bytes per HDMI pixclk > > - Ratio between dsi-clk and hdmi-pixelclk must be 3 so the DSI and > > HDMI are in sync. So from bandwidth pov there are no differences > > between: > > - HDMI: 74.25 MHz * 24 Bit = 1782.0 MBit/s > > - DSI: 891 MHz * 2 lanes = 1782.0 MBit/s (dsi-clock: 445.5 ) > > - DSI: 445.5 MHz * 4 lanes = 1782.0 MBit/s (dsi-clock: 222.75) > > > > But the ratio is different and therefore the faster clocking option > > let something 'overflow'. > > I'll agree that all looks consistent. > > > Anyway, but all this means that Adam should configure the > > burst-clock-rate to 445.5 and set the lanes to 4. But this doesn't work > > either and now we are back on my initial statement -> the driver needs > > some attention. > > Things always need attention :-) ^^ > I suspect that it's the use of the timing generator that is the issue. > The programming guide does recommend using it for all modes, so that > would be a sensible first step. But I tested it without the timing-generator too. Can you or Adam verify the timing-generator diable logic? > I will say that we had a number of issues getting this chip to do > anything, and it generally seemed happier on 2 or 3 lanes instead of > 4. Suffice to say that we abandoned trying to use it, despite some > assistance from ADI. Even more interessting, what is your alternative to this chip? Regards, Marco