Received: by 2002:a05:6358:e9c4:b0:b2:91dc:71ab with SMTP id hc4csp1462602rwb; Fri, 5 Aug 2022 02:18:59 -0700 (PDT) X-Google-Smtp-Source: AA6agR7EYJzz4hV6q4M0Jk7khClLl4Wi5nsTk73KPrQMZJcaph78r9ujHhW+kuJnKYqKM3lG6CwF X-Received: by 2002:a17:903:1207:b0:16c:7889:10bd with SMTP id l7-20020a170903120700b0016c788910bdmr5937579plh.164.1659691139605; Fri, 05 Aug 2022 02:18:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1659691139; cv=none; d=google.com; s=arc-20160816; b=tKET3ApaHya96CXr35jrRkU24chKJn+aMseDsDPoFaw7rvLXfaDAK2IRB665gSZx5v EzaS3GjX3AhBku1H9CJGqpTTfBGnwh7MKCeF9X6BSIVp93R/JWSTlOqwVr8AjIQVu9bj lMGglagRE2ErdQ3nIxVH8w7wFI+OzgacgsL09MLB31saLczJade9axI1be4ssQyfGOJu a4mCMCnuC132WwQgZ5mbtHqubkS1mdCFQY7P4Q1cKnxwrFxds0LjSQu+j1/FXUO4IDNk 7eKuqVv/l/nf6L9NYo6dVAA6iDn0HGd5jYiGIH2OXaCB0rHf7wRQ0bpHuIGHbDkeLzj6 mDLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=vznseDmUnuMb6hSQlOQoMoYu4mhbfl3+NrxCglswcr0=; b=xNsZow3q8B+KBewbgh0ngg3FK8TYkPgtMvUIkI+5xoUDqlp0Iy2ev8PKvvDdGinkDL bxUr5g3R/xHeIp3n6r5ADX+0IVL0iL3Tx+eLBCxcVdokRp6hpHreq2+9rKEkNaLksQxv nfG7RYPMRCipvkJPDoJBSnH5bDXUtrwh/UUloZflXwtMsuIVbiN62SeZZeC7fFijz9X0 HtN+6WlPtvy0HwWLaV9vEqpVqugjvHrxxC4yhuxVDU0sUowrIL4xUsWLuckf+dfL9qyr XbZgBazc0C1qTCuwJk9mtP9RLsxrH6+XGkoMaAGU149R4oJVudGldXjPdQwuLxyy5EEk CCxg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o7-20020a170902d4c700b0016bde614f40si4245952plg.253.2022.08.05.02.18.45; Fri, 05 Aug 2022 02:18:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232200AbiHEI66 (ORCPT + 99 others); Fri, 5 Aug 2022 04:58:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234856AbiHEI6z (ORCPT ); Fri, 5 Aug 2022 04:58:55 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C543B74E26; Fri, 5 Aug 2022 01:58:53 -0700 (PDT) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.9; Fri, 5 Aug 2022 16:58:51 +0800 From: Yu Tu To: , , , , , Rob Herring , Neil Armstrong , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl CC: Yu Tu Subject: [PATCH V3 0/6] Add S4 SoC PLL and Peripheral clock controller Date: Fri, 5 Aug 2022 16:57:10 +0800 Message-ID: <20220805085716.5635-1-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.18.11.248] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 1. Add PLL and Peripheral clock controller driver for S4 SOC. Yu Tu (6): dt-bindings: clock: meson: add S4 SoC PLL clock controller bindings arm64: dts: meson: add S4 Soc PLL clock controller in DT clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver dt-bindings: clk: meson: add S4 SoC peripheral clock controller bindings arm64: dts: meson: add S4 Soc Peripheral clock controller in DT clk: meson: s4: add s4 SoC peripheral clock controller driver V2 -> V3: Use two clock controller. V1 -> V2: Change format as discussed in the email. Link:https://lore.kernel.org/all/20220728054202.6981-1-yu.tu@amlogic.com/ .../bindings/clock/amlogic,s4-clkc.yaml | 92 + .../bindings/clock/amlogic,s4-pll-clkc.yaml | 51 + MAINTAINERS | 1 + arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 34 + drivers/clk/meson/Kconfig | 25 + drivers/clk/meson/Makefile | 2 + drivers/clk/meson/s4-pll.c | 891 ++++ drivers/clk/meson/s4-pll.h | 88 + drivers/clk/meson/s4.c | 3878 +++++++++++++++++ drivers/clk/meson/s4.h | 232 + include/dt-bindings/clock/amlogic,s4-clkc.h | 131 + .../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 + 12 files changed, 5455 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-clkc.yaml create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml create mode 100644 drivers/clk/meson/s4-pll.c create mode 100644 drivers/clk/meson/s4-pll.h create mode 100644 drivers/clk/meson/s4.c create mode 100644 drivers/clk/meson/s4.h create mode 100644 include/dt-bindings/clock/amlogic,s4-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h base-commit: 08fc500fe3d4b1f0603fb97ad353f246a3d52d2d -- 2.33.1