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From:   Vadym Kochan <vadym.kochan@plvision.eu>
To:     Hu Ziji <huziji@marvell.com>, Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Vadym Kochan <vadym.kochan@plvision.eu>,
        linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Elad Nachman <enachman@marvell.com>
Subject: [PATCH 3/3] arm64: dts: marvell: Add DTSI to fix Xenon SDHCI 2G limitation on AC5 SoC
Date:   Sat,  6 Aug 2022 11:58:14 +0300
Message-Id: <20220806085818.9873-4-vadym.kochan@plvision.eu>
In-Reply-To: <20220806085818.9873-1-vadym.kochan@plvision.eu>
References: <20220806085818.9873-1-vadym.kochan@plvision.eu>
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There is a limitation in Xenon SDHCI on AC5 SoC that it can address only
the first 2G of memory, so it was decided to use reserved-memory as
bounce buffer because swiotlb=force and SDMA mode did not help.

There is a custom property which is used to attach bounce memory region
to the device on demand (only if more 2G memory is used). This is a software
property only so it was not described in the dt-bindings.

Separate DTSI is added to reserve memory only for boards with eMMC cards.

Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu>
---
 .../boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi  | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi

diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi
new file mode 100644
index 000000000000..cc5e53b64473
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Include file for AC5 with SDHCI support
+ *
+ * Copyright (C) 2022 Marvell
+ */
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * SDHCI controller in AC5 SoC has 2G address space
+		 * limitation, so in case if RAM has more 2G then use
+		 * this dedicated memory region.
+		 */
+		sdhci_dma_restricted_region: sdhci-dma-restricted-region@0 {
+			compatible = "restricted-dma-pool";
+			reg = <0x2 0x0 0x0 0x200000>;
+		};
+	};
+
+	sdhci_dma_bounce_pool: sdhci-dma-bounce-pool@0 {
+		memory-region = <&sdhci_dma_restricted_region>;
+	};
+
+	soc {
+		sdhci: sdhci@805c0000 {
+			compatible = "marvell,ac5-sdhci";
+			reg = <0x0 0x805c0000 0x0 0x300>;
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cnm_clock>;
+			clock-names = "core";
+			marvell,ac5-sdhci-dma-bounce-pool = <&sdhci_dma_bounce_pool>;
+			status = "okay";
+		};
+	};
+};
-- 
2.17.1