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From:   Vadym Kochan <vadym.kochan@plvision.eu>
To:     Hu Ziji <huziji@marvell.com>, Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Vadym Kochan <vadym.kochan@plvision.eu>,
        linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Elad Nachman <enachman@marvell.com>
Subject: [PATCH 0/3] mmc: xenon-sdhci: Try to fix 2G address limitation on AC5 SoC
Date:   Sat,  6 Aug 2022 11:58:11 +0300
Message-Id: <20220806085818.9873-1-vadym.kochan@plvision.eu>
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There is a limitation on AC5 SoC that Xenon SDHC can address only
first 2GB of memory. Turning to the SDMA mode to use the bounce_buffer
causes ext_csd recognition to fail on init.

Using of swiotlb=force also does not help as it is allocated at the
end of the memory.

So it was decided to use reserved-memory as a bounce buffer in case
if the board has more than 2G of memory, or turn on the PIO
mode if such memory region does not exist in the device-tree.
There is a custom property which is used to attach bounce memory region
to the device on demand (only if more 2G memory is used). This is a software
property only so it was not described in the dt-bindings.

Separate DTSI is added to reserve memory only for boards with eMMC cards.

It was tested that this approach is 1.5 times faster than PIO.

Vadym Kochan (3):
  dt-bindings: mmc: xenon: Add compatible string for Xenon SDHCI on AC5
    SoC
  mmc: sdhci-xenon: Try to fix 2G address limitation on AC5 SoC
  arm64: dts: marvell: Add DTSI to fix Xenon SDHCI 2G limitation on AC5
    SoC

 .../bindings/mmc/marvell,xenon-sdhci.yaml     |  3 ++
 .../boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi  | 40 +++++++++++++++++++
 drivers/mmc/host/sdhci-xenon.c                | 36 +++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx25xx-sdhci.dtsi

-- 
2.17.1