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Message-ID: <cb74b5e0-2243-5afc-dd8e-7b024ca3e3da@linaro.org>
Date:   Mon, 8 Aug 2022 12:21:36 +0300
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Subject: Re: [PATCH 3/3] arm64: dts: marvell: Add DTSI to fix Xenon SDHCI 2G
 limitation on AC5 SoC
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To:     Vadym Kochan <vadym.kochan@plvision.eu>,
        Hu Ziji <huziji@marvell.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Cc:     Elad Nachman <enachman@marvell.com>
References: <20220806085818.9873-1-vadym.kochan@plvision.eu>
 <20220806085818.9873-4-vadym.kochan@plvision.eu>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20220806085818.9873-4-vadym.kochan@plvision.eu>
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On 06/08/2022 11:58, Vadym Kochan wrote:
> +
> +	soc {
> +		sdhci: sdhci@805c0000 {
> +			compatible = "marvell,ac5-sdhci";
> +			reg = <0x0 0x805c0000 0x0 0x300>;
> +			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cnm_clock>;
> +			clock-names = "core";
> +			marvell,ac5-sdhci-dma-bounce-pool = <&sdhci_dma_bounce_pool>;

Undocumented property.

Best regards,
Krzysztof