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Message-ID: <750f836b-2e31-da48-3c72-94be44efb9e4@intel.com>
Date:   Mon, 8 Aug 2022 13:52:07 -0700
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Subject: Re: [RFC PATCH 0/2] cxl: BG operations and device sanitation
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To:     Davidlohr Bueso <dave@stgolabs.net>
Cc:     linux-cxl@vger.kernel.org, dan.j.williams@intel.com,
        bwidawsk@kernel.org, Jonathan.Cameron@huawei.com,
        ira.weiny@intel.com, alison.schofield@intel.com,
        vishal.l.verma@intel.com, a.manzanares@samsung.com,
        mcgrof@kernel.org, linux-kernel@vger.kernel.org
References: <20220804045029.2905056-1-dave@stgolabs.net>
 <bcbe1db2-cb8e-1889-2888-f4618d749bd4@intel.com>
 <20220804200712.gaiswmkjsa3pnkc5@offworld>
From:   Dave Jiang <dave.jiang@intel.com>
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On 8/4/2022 1:07 PM, Davidlohr Bueso wrote:
> On Thu, 04 Aug 2022, Dave Jiang wrote:
>
>> From the operational sense everything looks good to me. As for the
>> polling delay on overwrite, with pre-CXL pmem on Optane, we've
>> discovered that overwrite can take a long time depending on the size.
>> Sometimes MANY hours if the size is really large. We just opted to
>> increment the polling interval as time went on [1] instead of based on
>> size.
>
> Thanks for having a look. Sure, we can do that, I have no particular 
> attachment
> to doing it based on size (it's just the way it occured to me). I am 
> curious,
> though: While regardless of size vs time based estimates, are the numbers
> expected to be similar for volatile regions? All these numbers being from
> nvdimm DSM docs.

I don't either. Just pointing out that's what we did with the Optane 
stuff. I think that the volatile devices (DRAM?) would probably be a lot 
faster when it comes to writes. So maybe won't take as long. And also 
perhaps smaller in size in the immediate future? Just guessing.


>
> Thanks,
> Davidlohr