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Shutemov" , "H. Peter Anvin" , Michael Roth , Joerg Roedel , Andy Lutomirski , Peter Zijlstra References: <20220614120231.48165-1-kirill.shutemov@linux.intel.com> <21d5d55640ee1c5d66501b9398858b6a6bd6546f.1659978985.git.thomas.lendacky@amd.com> <50599c3c-eacb-7774-746c-021adf3f56e3@intel.com> <6b615140-4075-4fab-de23-e0c7cd3c64d8@amd.com> <77087e5b-ae81-8809-bf37-448d18c7b618@intel.com> From: Tom Lendacky In-Reply-To: <77087e5b-ae81-8809-bf37-448d18c7b618@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SN4PR0501CA0043.namprd05.prod.outlook.com (2603:10b6:803:41::20) To DM4PR12MB5229.namprd12.prod.outlook.com (2603:10b6:5:398::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e3ead0cb-495b-4a9b-97d6-08da798e45e5 X-MS-TrafficTypeDiagnostic: BL1PR12MB5048:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3g+vAI6xsfrYQvLelxpLsUUtZ8I211Q2gza4DEgtX1eYiYWJNeRtrNpUYBOwzeoR+/3PmlV8RCMsRw9g+W62XOKT61s7JPzsXUg2tUYoBl5DNinLaTyRKnXEX1dWPv24MLKBUrxq8pa/LNEhWCKgKoQ07b6FaTbRRSS0Gh8h1itIbKclh5SlEpc+n6fiUdfBllQlQFdNmklg4qaD3krIS8CIP9AupE1lvSTVgXXqK/OGHn0ZskFhLSvtM09hACJFkPXgNUE7i1I+iWKHQnZd6X7bzUkrzMMF6+3q100Aw1EBFgGJCqd2C0qZqaeieOImHqtG3/Bkpu6IXkG0yd4vIHhr7HZkv9TpuN7jnKkt1fRrm2H8BPJyb4ioPP5O/q4ryxwDT6uBrl22987GK6A8BfJ2Z1duYv4z2AFp3+yKSObi1ShX0y2FWQ9tJ/5zX4bIgBS1WfT98H75uIw27WS9AZQgyh38407/GHJD35TGUjQlqV+m1YQYc3SfuMtUMqMyYPK/Z0U504W0Fz+2M7OXmOeR5uzhVzLd6plctVEnl5ykTuRhGe3ymIYCfhW1Ih0QVjkRJ/y15TxOoj2S1xiRRGpcUX62skAjMNCJMprvOH6EJlRC4M5eakqXsZo9o0ZcYgaGnvK+ibvmapI8TN3G8w50eBq1IGx/8RoCZWpxINjEiXtlg0lR8N+TK+LAd+92KxDCevs5NMywtmJTFInLIk3lzZJEu6Yblk93meYU7gvDoM2MYESh2i+gVDiNliCzQLGkkUQO5O1OJ9YqB8GITsRIcxJE8mgV4xjM7vHcXy4ft3GY3hMgOtfSuS45hqHbq0nlpJOAM4Cikfu/u75Fgw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM4PR12MB5229.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(39860400002)(136003)(396003)(366004)(376002)(346002)(6512007)(86362001)(2616005)(186003)(38100700002)(31696002)(5660300002)(31686004)(7416002)(2906002)(316002)(4326008)(8676002)(54906003)(66476007)(36756003)(8936002)(66946007)(66556008)(6506007)(53546011)(6666004)(41300700001)(478600001)(6486002)(26005)(43740500002)(45980500001);DIR:OUT;SFP:1101; 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>>> >>> So, there's a code path that can't be entered until this is set?  Seems >>> like the least we can do it annotate that path with a >>> WARN_ON_ONCE(!ghcb_percpu_ready). >> >> Sure, that can be added. Right now the only function that calls >> vmgexit_psc() is covered (set_pages_state()/__set_pages_state()) and is >> doing the right thing. But I guess if anything is added in the future, >> that will provide details on what happened. >> >>> >>> Also, how does having _one_ global variable work for indicating the >>> state of multiple per-cpu structures?  The code doesn't seem to delay >>> setting this variable until after _all_ of the per-cpu state is ready. >> >> All of the per-CPU GHCBs are allocated during the BSP boot, before any >> AP is started. The APs only ever run the kernel_exc_vmm_communication() >> #VC handler and only ever use the per-CPU version of the GHCB, never the >> early boot version. This is based on the initial_vc_handler being >> switched to the runtime #VC handler, kernel_exc_vmm_communication. >> >> The trigger for the switch over for the BSP from the early boot GHCB to >> the per-CPU GHCB is during setup_ghcb() after the initial_vc_handler has >> been switched to kernel_exc_vmm_communication, which is just after the >> per-CPU allocations. By putting the setting of the ghcb_percpu_ready in >> setup_ghcb(), it indicates that the BSP per-CPU GHCB has been registered >> and can be used. > > That description makes the proposed comment even more confusing: > > /* Flag to indicate when the first per-CPU GHCB is registered */ > > The important thing is that this variable is only _useful_ for the boot > CPU. After the boot CPU has allocated space for _itself_, it can then > go and stop using the MSR-based method. > > The reason it's set after "the first" is because "the first" is also the > boot CPU, but referring to it as the "the first" is a bit oblique. > Maybe something like this: > > /* > * Set after the boot CPU's GHCB is registered. At that point, > * it can be used for calls instead of MSRs. > */ Sure, I'll work on the wording. Thanks, Tom