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Tue, 09 Aug 2022 09:52:46 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6F35A10002A; Tue, 9 Aug 2022 09:52:44 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E68AC216EEE; Tue, 9 Aug 2022 09:52:44 +0200 (CEST) Received: from [10.201.21.72] (10.75.127.50) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Tue, 9 Aug 2022 09:52:44 +0200 Message-ID: Date: Tue, 9 Aug 2022 09:52:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/3] dt-bindings: spi: stm32: Add st,dual-flash property in st,stm32-qspi.yaml Content-Language: en-US To: Krzysztof Kozlowski , Mark Brown , Alexandre Torgue , , CC: , , , , , References: <20220808074051.44736-1-patrice.chotard@foss.st.com> <20220808074051.44736-2-patrice.chotard@foss.st.com> <9ad4b4a8-988e-f185-f80c-6f15f341ce8c@linaro.org> <79fd7e19-ceef-14fb-5a83-603740735f8f@foss.st.com> <38c3977a-0196-1832-ff94-317064cbc439@linaro.org> From: Patrice CHOTARD In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.50] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-09_03,2022-08-09_01,2022-06-22_01 X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,NICE_REPLY_A,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzystof On 8/9/22 07:29, Krzysztof Kozlowski wrote: > On 09/08/2022 07:18, Krzysztof Kozlowski wrote: >> On 08/08/2022 19:08, Patrice CHOTARD wrote: >>> Hi Krzystof >>> >>> On 8/8/22 11:01, Krzysztof Kozlowski wrote: >>>> On 08/08/2022 10:40, patrice.chotard@foss.st.com wrote: >>>>> From: Patrice Chotard >>>>> >>>>> Add new property st,dual-flash which allows to use the QSPI interface as a >>>>> communication channel using up to 8 qspi line. >>>>> This mode can only be used if cs-gpios property is defined. >>>>> >>>>> Signed-off-by: Patrice Chotard >>>>> --- >>>>> Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 8 ++++++++ >>>>> 1 file changed, 8 insertions(+) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml >>>>> index 6ec6f556182f..5e4f9109799e 100644 >>>>> --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml >>>>> +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml >>>>> @@ -46,6 +46,14 @@ properties: >>>>> - const: tx >>>>> - const: rx >>>>> >>>>> + st,dual-flash: >>>>> + type: boolean >>>>> + description: >>>>> + Allows to use 8 data lines in case cs-gpios property is defined. >>>> >>>> It's named dual-flash, but what if you want to use QSPI to connect for >>>> example to FPGA? >>>> >>>> Also how is this related to parallel-memories property? >>> >>> I called it "dual-flash" simply because it enable the dual flash feature of the QSPI block (bit CR_DFM : Dual Flash Mode) >>> which allows to use the 8 lines simultaneously of our dual QSPI block. >> >> And how is it related to existing parallel-memories property? > > Maybe I was not specific enough, so let me rephrase - we have already > parallel-memories property. How this one is different (to justify the > new property)? Is just one memory connected in your case to QSPI over 8 > data lines? Our QSPI block is a dual Quad-SPI memory interface, it can managed 2 QSPI flashes independently. There is a specific mode, dual flash mode, where the 2 QSPI flashes can be accessed simultaneously using 8 data lines. In this case, both throughput and capacity are two fold with this mode. To illustrate, you can have a look at STM32MP157 reference manual (chapter 27.3.1 figure 172) available here: https://www.st.com/resource/en/reference_manual/rm0436-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf As you mentioned above, the goal is to connect a FPGA to this 8 lines bus. Hope it clarifies enough ;-) Thanks Patrice > > Best regards, > Krzysztof