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Date:   Tue, 9 Aug 2022 16:27:30 +0100
From:   Mark Brown <broonie@kernel.org>
To:     Neil Armstrong <narmstrong@baylibre.com>
Cc:     linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
        Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Message-ID: <YvJ84qkuXdvVgXRm@sirena.org.uk>
References: <20220809152019.461741-1-narmstrong@baylibre.com>
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On Tue, Aug 09, 2022 at 05:20:19PM +0200, Neil Armstrong wrote:
> At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(),
> this resets the SPICC_CONREG register and notably the value set by the
> Common Clock Framework.

> This saves the datarate dividor value between message to keep the last
> set value by the Common Clock Framework.

When you say the value set by the clock framework does that mean that
the clock driver is adjusting hardware inside the SPI controller IP
block which is then getting reset by the SPI driver without the SPI
driver knowing about it?  That seems like a bad idea as you're finding
here.

> This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support")
> because we recalculated and wrote the rate for each xfer.

Note that the rate might change per transfer.

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