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Date:   Tue, 9 Aug 2022 16:19:49 -0500
From:   Bjorn Andersson <bjorn.andersson@linaro.org>
To:     Satya Priya <quic_c_skakit@quicinc.com>
Cc:     Rob Herring <robh@kernel.org>,
        Douglas Anderson <dianders@chromium.org>,
        Stephen Boyd <swboyd@chromium.org>,
        Andy Gross <agross@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        Taniya Das <quic_tdas@quicinc.com>
Subject: Re: [PATCH V7 1/5] dt-bindings: clock: Add "qcom,adsp-pil-mode"
 property
Message-ID: <YvLPdVv2/7pJLeru@baldur>
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On Wed 27 Jul 03:27 CDT 2022, Satya Priya wrote:

> The LPASS Peripheral loader clocks would be used to bring
> LPASS out of reset, when this property is present.
> 

Can you please elaborate on what you mean here?

When this property is set you assume that remoteproc is used to boot the
LPASS and therefor some clocks should be handled differently?

This needs to be written in a way that someone outside of your project
can understand the purpose.

> This is a cleanup done to handle overlap of regmap of
> lpasscc and lpass_aon blocks. As a part of this, remove
> the "cc" regmap from lpasscc node.
> 

"regmap" is an implementation detail, the binding change should describe
the changes to the representation of the hardware description.

Thanks,
Bjorn

> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> ---
>  Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml   | 6 ++----
>  .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml         | 7 +++++++
>  2 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> index 47028d7..633887d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> @@ -36,13 +36,11 @@ properties:
>      items:
>        - description: LPASS qdsp6ss register
>        - description: LPASS top-cc register
> -      - description: LPASS cc register
>  
>    reg-names:
>      items:
>        - const: qdsp6ss
>        - const: top_cc
> -      - const: cc
>  
>  required:
>    - compatible
> @@ -59,8 +57,8 @@ examples:
>      #include <dt-bindings/clock/qcom,lpass-sc7280.h>
>      clock-controller@3000000 {
>        compatible = "qcom,sc7280-lpasscc";
> -      reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
> -      reg-names = "qdsp6ss", "top_cc", "cc";
> +      reg = <0x03000000 0x40>, <0x03c04000 0x4>;
> +      reg-names = "qdsp6ss", "top_cc";
>        clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
>        clock-names = "iface";
>        #clock-cells = <1>;
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
> index bad9135..5ccfb24 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
> @@ -41,6 +41,12 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  qcom,adsp-pil-mode:
> +    description:
> +      Indicates if the LPASS would be brought out of reset using
> +      peripheral loader.
> +    type: boolean
> +
>  required:
>    - compatible
>    - reg
> @@ -165,6 +171,7 @@ examples:
>        clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
>                 <&lpasscore LPASS_CORE_CC_CORE_CLK>;
>        clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
> +      qcom,adsp-pil-mode;
>        #clock-cells = <1>;
>        #power-domain-cells = <1>;
>      };
> -- 
> 2.7.4
>