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From:   =?utf-8?Q?Bj=C3=B8rn_Mork?= <bjorn@mork.no>
To:     Slark Xiao <slark_xiao@163.com>
Cc:     davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
        pabeni@redhat.com, netdev@vger.kernel.org,
        linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] net: usb: qmi_wwan: Add support for Cinterion MV32
Organization: m
References: <20220810014521.9383-1-slark_xiao@163.com>
Date:   Wed, 10 Aug 2022 08:55:42 +0200
In-Reply-To: <20220810014521.9383-1-slark_xiao@163.com> (Slark Xiao's message
        of "Wed, 10 Aug 2022 09:45:21 +0800")
Message-ID: <8735e4mvtd.fsf@miraculix.mork.no>
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Slark Xiao <slark_xiao@163.com> writes:

> There are 2 models for MV32 serials. MV32-W-A is designed
> based on Qualcomm SDX62 chip, and MV32-W-B is designed based
> on Qualcomm SDX65 chip. So we use 2 different PID to separate it.
>
> Test evidence as below:
> T:  Bus=3D03 Lev=3D01 Prnt=3D01 Port=3D02 Cnt=3D03 Dev#=3D  3 Spd=3D480 M=
xCh=3D 0
> D:  Ver=3D 2.10 Cls=3Def(misc ) Sub=3D02 Prot=3D01 MxPS=3D64 #Cfgs=3D  1
> P:  Vendor=3D1e2d ProdID=3D00f3 Rev=3D05.04
> S:  Manufacturer=3DCinterion
> S:  Product=3DCinterion PID 0x00F3 USB Mobile Broadband
> S:  SerialNumber=3Dd7b4be8d
> C:  #Ifs=3D 4 Cfg#=3D 1 Atr=3Da0 MxPwr=3D500mA
> I:  If#=3D0x0 Alt=3D 0 #EPs=3D 3 Cls=3Dff(vend.) Sub=3Dff Prot=3D50 Drive=
r=3Dqmi_wwan
> I:  If#=3D0x1 Alt=3D 0 #EPs=3D 3 Cls=3Dff(vend.) Sub=3Dff Prot=3D40 Drive=
r=3Doption
> I:  If#=3D0x2 Alt=3D 0 #EPs=3D 3 Cls=3Dff(vend.) Sub=3Dff Prot=3D40 Drive=
r=3Doption
> I:  If#=3D0x3 Alt=3D 0 #EPs=3D 2 Cls=3Dff(vend.) Sub=3Dff Prot=3D30 Drive=
r=3Doption

The patch looks nice, but I have a couple of questions since you're one
of the first pushing one of these SDX6x modems.

Is that protocol pattern fixed on this generation of Qualcomm chips?  It
looks like an extension of what they started with the SDX55 generation,
where the DIAG port was identified by ff/ff/30 across multiple vendors.

Specifically wrt this driver and patch, I wonder if we can/should match
on ff/ff/50 instead of interface number here?  I note that the interface
numbers are allocated sequentionally. Probably in the order these
function are enabled by the firmware? If so, are we sure this is static?
Or could we risk config variants where the RMNET/QMI function have a
different interface number for the same PIDs?

And another possibility you might consider.  Assuming that ff/ff/50
uniquely identifies RMNET/QMI functions regardless of PID, would you
consider a VID+class match to catch all of them?  This would not only
support both the PIDs of this patch in one go, but also any future PIDs
without the need for further driver patches.


Bj=C3=B8rn