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Date:   Wed, 10 Aug 2022 10:26:43 -0300
From:   Arnaldo Carvalho de Melo <acme@kernel.org>
To:     Ravi Bangoria <ravi.bangoria@amd.com>
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com>,
        Jiri Olsa <olsajiri@gmail.com>,
        Namhyung Kim <namhyung@kernel.org>,
        Stephane Eranian <eranian@google.com>,
        Ian Rogers <irogers@google.com>, Joe Mario <jmario@redhat.com>,
        Leo Yan <leo.yan@linaro.org>, Ali Saidi <alisaidi@amazon.com>,
        Andi Kleen <ak@linux.intel.com>,
        Kan Liang <kan.liang@linux.intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>, X86 ML <x86@kernel.org>,
        linux-perf-users <linux-perf-users@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Sandipan Das <sandipan.das@amd.com>, ananth.narayan@amd.com,
        Kim Phillips <kim.phillips@amd.com>, santosh.shukla@amd.com
Subject: Re: [PATCH v2 00/14] perf mem/c2c: Add support for AMD
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Em Fri, Jul 22, 2022 at 07:51:27AM +0530, Ravi Bangoria escreveu:
> On 21-Jul-22 10:54 PM, Arnaldo Carvalho de Melo wrote:
> > On Mon, Jul 18, 2022, 12:34 PM Arnaldo Carvalho de Melo <arnaldo.melo@gmail.com> wrote:
> >> Em Tue, Jul 12, 2022 at 01:35:25PM +0200, Jiri Olsa escreveu:
> >>> On Thu, Jun 16, 2022 at 05:06:23PM +0530, Ravi Bangoria wrote:
> >>>> Perf mem and c2c tools are wrappers around perf record with mem load/
> >>>> store events. IBS tagged load/store sample provides most of the
> >>>> information needed for these tools. Enable support for these tools on
> >>>> AMD Zen processors based on IBS Op pmu.

> >>>> Ravi Bangoria (14):
> >>>>   perf/mem: Introduce PERF_MEM_LVLNUM_{EXTN_MEM|IO}
> >>>>   perf/x86/amd: Add IBS OP_DATA2 DataSrc bit definitions
> >>>>   perf/x86/amd: Support PERF_SAMPLE_DATA_SRC
> >>>>   perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT}
> >>>>   perf/x86/amd: Support PERF_SAMPLE_ADDR
> >>>>   perf/x86/amd: Support PERF_SAMPLE_PHY_ADDR
> >>>>   perf tool: Sync include/uapi/linux/perf_event.h header
> >>>>   perf tool: Sync arch/x86/include/asm/amd-ibs.h header
> >>>>   perf mem: Add support for printing PERF_MEM_LVLNUM_{EXTN_MEM|IO}
> >>>>   perf mem/c2c: Set PERF_SAMPLE_WEIGHT for LOAD_STORE events
> >>>>   perf mem/c2c: Add load store event mappings for AMD
> >>>>   perf mem/c2c: Avoid printing empty lines for unsupported events
> >>>>   perf mem: Use more generic term for LFB
> >>>>   perf script: Add missing fields in usage hint

> >>> tools part looks good to me

> >>> Acked-by: Jiri Olsa <jolsa@kernel.org>

> >> What about the kernel bits? PeterZ? Is this in some tip branch?

> Peter, Would you able to pick this up for next merge window? Please
> note that, one dependency patch needs to be applied first from "IBS
> Zen4 enhancement" series:
 
> [PATCH v6 6/8] perf/x86/ibs: Add new IBS register bits into header
> https://lore.kernel.org/lkml/20220604044519.594-7-ravi.bangoria@amd.com

It is there already:

⬢[acme@toolbox perf]$ git log --oneline torvalds/master | grep -m1 "Add new IBS register bits into header"
326ecc15c61c349c perf/x86/ibs: Add new IBS register bits into header
⬢[acme@toolbox perf]$

but not the other patches in this series:

⬢[acme@toolbox perf]$ git log --oneline torvalds/master | grep -m1 "amd: Support PERF_SAMPLE_PHY_ADDR"
⬢[acme@toolbox perf]$

- Arnaldo