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Message-ID: <dd173944-80d3-e13f-c405-f076401bf6c7@linaro.org>
Date:   Wed, 10 Aug 2022 16:29:36 +0300
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Subject: Re: [PATCH] riscv: dts: microchip: add qspi compatible fallback
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To:     Conor Dooley <conor.dooley@microchip.com>,
        Daire McNamara <daire.mcnamara@microchip.com>
Cc:     nagasuresh.relli@microchip.com,
        valentina.fernandezalanis@microchip.com, broonie@kernel.org,
        devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org,
        robh+dt@kernel.org, linux-kernel@vger.kernel.org,
        linux-spi@vger.kernel.org, linux-riscv@lists.infradead.org
References: <20220810085914.801170-1-conor.dooley@microchip.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20220810085914.801170-1-conor.dooley@microchip.com>
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On 10/08/2022 11:59, Conor Dooley wrote:
> The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
> of the FPGA IP core. The original binding had no fallback etc, so this
> device tree is valid as is. There was also no functional driver for the
> QSPI IP, so no device with a devicetree from a previous mainline
> release will regress.
> 
> Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> See the link for binding discussion. I'll apply this at some point once


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof