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References: <20220726182152.123649-1-andrealmeid@igalia.com> <20220726182152.123649-3-andrealmeid@igalia.com>
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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Wed, 10 Aug 2022 11:54:59 -0400
Message-ID: <CADnq5_N45m1Ce76bX6VnLWE6GgsqGCdmWmrSvgjEF=meEWf-jQ@mail.gmail.com>
Subject: Re: [PATCH v2 2/4] drm/amd/pm: Implement GFXOFF's entry count and
 residency for vangogh
To:     =?UTF-8?Q?Andr=C3=A9_Almeida?= <andrealmeid@igalia.com>
Cc:     Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        Pan Xinhui <Xinhui.Pan@amd.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Hawking Zhang <Hawking.Zhang@amd.com>,
        Tao Zhou <tao.zhou1@amd.com>,
        Felix Kuehling <Felix.Kuehling@amd.com>,
        Jack Xiao <Jack.Xiao@amd.com>, amd-gfx@lists.freedesktop.org,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
        Tom St Denis <tom.stdenis@amd.com>,
        Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
        kernel-dev@igalia.com
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On Tue, Jul 26, 2022 at 2:23 PM Andr=C3=A9 Almeida <andrealmeid@igalia.com>=
 wrote:
>
> Implement functions to get and set GFXOFF's entry count and residency
> for vangogh.
>
> Signed-off-by: Andr=C3=A9 Almeida <andrealmeid@igalia.com>
> ---
>  .../pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h    |  5 +-
>  drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  |  5 +-
>  .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 92 +++++++++++++++++++
>  3 files changed, 100 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h b=
/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> index fe130a497d6c..7471e2df2828 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_5_ppsmc.h
> @@ -108,7 +108,10 @@
>  #define PPSMC_MSG_SetSlowPPTLimit                      0x4A
>  #define PPSMC_MSG_GetFastPPTLimit                      0x4B
>  #define PPSMC_MSG_GetSlowPPTLimit                      0x4C
> -#define PPSMC_Message_Count                            0x4D
> +#define PPSMC_MSG_GetGfxOffStatus                     0x50
> +#define PPSMC_MSG_GetGfxOffEntryCount                 0x51
> +#define PPSMC_MSG_LogGfxOffResidency                  0x52
> +#define PPSMC_Message_Count                            0x53
>
>  //Argument for PPSMC_MSG_GfxDeviceDriverReset
>  enum {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/d=
rm/amd/pm/swsmu/inc/smu_types.h
> index 19084a4fcb2b..76fb6cbbc09c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> @@ -235,7 +235,10 @@
>         __SMU_DUMMY_MAP(UnforceGfxVid),           \
>         __SMU_DUMMY_MAP(HeavySBR),                      \
>         __SMU_DUMMY_MAP(SetBadHBMPagesRetiredFlagsPerChannel), \
> -       __SMU_DUMMY_MAP(EnableGfxImu),
> +       __SMU_DUMMY_MAP(EnableGfxImu),                  \
> +       __SMU_DUMMY_MAP(GetGfxOffStatus),                \
> +       __SMU_DUMMY_MAP(GetGfxOffEntryCount),            \
> +       __SMU_DUMMY_MAP(LogGfxOffResidency),
>
>  #undef __SMU_DUMMY_MAP
>  #define __SMU_DUMMY_MAP(type)  SMU_MSG_##type
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/g=
pu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 89504ff8e9ed..4e547573698b 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -138,6 +138,9 @@ static struct cmn2asic_msg_mapping vangogh_message_ma=
p[SMU_MSG_MAX_COUNT] =3D {
>         MSG_MAP(SetSlowPPTLimit,                    PPSMC_MSG_SetSlowPPTL=
imit,                                          0),
>         MSG_MAP(GetFastPPTLimit,                    PPSMC_MSG_GetFastPPTL=
imit,                                          0),
>         MSG_MAP(GetSlowPPTLimit,                    PPSMC_MSG_GetSlowPPTL=
imit,                                          0),
> +       MSG_MAP(GetGfxOffStatus,                    PPSMC_MSG_GetGfxOffSt=
atus,                                          0),
> +       MSG_MAP(GetGfxOffEntryCount,                PPSMC_MSG_GetGfxOffEn=
tryCount,                                      0),
> +       MSG_MAP(LogGfxOffResidency,                 PPSMC_MSG_LogGfxOffRe=
sidency,                                       0),
>  };
>
>  static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUN=
T] =3D {
> @@ -2200,6 +2203,92 @@ static int vangogh_set_power_limit(struct smu_cont=
ext *smu,
>         return ret;
>  }
>
> +/**
> + * vangogh_set_gfxoff_residency
> + *
> + * @smu: amdgpu_device pointer
> + * @start: start/stop residency log
> + *
> + * This function will be used to log gfxoff residency
> + *
> + *
> + * Returns standard response codes.
> + */
> +static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool st=
art)
> +{
> +       int ret =3D 0;
> +       u32 residency;
> +       struct amdgpu_device *adev =3D smu->adev;
> +
> +       switch (adev->ip_versions[MP1_HWIP][0]) {
> +       case IP_VERSION(11, 5, 0):

Minor nit, but you can drip the IP version checks here.  This whole
file is specific to 11.5.

> +               if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> +                       return 0;
> +               ret =3D smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogG=
fxOffResidency,
> +                                                     start, &residency);
> +               if (!start)
> +                       adev->gfx.gfx_off_residency =3D residency;
> +               break;
> +       default:
> +               break;
> +       }
> +
> +       return ret;
> +}
> +
> +/**
> + * vangogh_get_gfxoff_residency
> + *
> + * @smu: amdgpu_device pointer
> + *
> + * This function will be used to get gfxoff residency.
> + *
> + * Returns standard response codes.
> + */
> +static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_=
t *residency)
> +{
> +       int ret =3D 0;
> +       struct amdgpu_device *adev =3D smu->adev;
> +
> +       switch (adev->ip_versions[MP1_HWIP][0]) {
> +       case IP_VERSION(11, 5, 0):

Same here.

> +               *residency =3D adev->gfx.gfx_off_residency;
> +               break;
> +       default:
> +               break;
> +       }
> +
> +       return ret;
> +}
> +
> +/**
> + * vangogh_get_gfxoff_entrycount - get gfxoff entry count
> + *
> + * @smu: amdgpu_device pointer
> + *
> + * This function will be used to get gfxoff entry count
> + *
> + * Returns standard response codes.
> + */
> +static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64=
_t *entrycount)
> +{
> +       int ret =3D 0, value =3D 0;
> +       struct amdgpu_device *adev =3D smu->adev;
> +
> +       switch (adev->ip_versions[MP1_HWIP][0]) {
> +       case IP_VERSION(11, 5, 0):
> +               if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> +                       return 0;
> +               ret =3D smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryC=
ount, &value);
> +               *entrycount =3D value + adev->gfx.gfx_off_entrycount;
> +               break;
> +       default:
> +               break;
> +       }
> +
> +       return ret;
> +}
> +
>  static const struct pptable_funcs vangogh_ppt_funcs =3D {
>
>         .check_fw_status =3D smu_v11_0_check_fw_status,
> @@ -2237,6 +2326,9 @@ static const struct pptable_funcs vangogh_ppt_funcs=
 =3D {
>         .mode2_reset =3D vangogh_mode2_reset,
>         .gfx_off_control =3D smu_v11_0_gfx_off_control,
>         .get_gfx_off_status =3D vangogh_get_gfxoff_status,
> +       .get_gfx_off_entrycount =3D vangogh_get_gfxoff_entrycount,
> +       .get_gfx_off_residency =3D vangogh_get_gfxoff_residency,
> +       .set_gfx_off_residency =3D vangogh_set_gfxoff_residency,
>         .get_ppt_limit =3D vangogh_get_ppt_limit,
>         .get_power_limit =3D vangogh_get_power_limit,
>         .set_power_limit =3D vangogh_set_power_limit,
> --
> 2.37.1
>