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charset=utf-8 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Krzysztof, On Thu, Aug 11, 2022 at 11:53:19AM +0300, Krzysztof Kozlowski wrote: > On 11/08/2022 11:44, Markus Schneider-Pargmann wrote: > > From: Fabien Parent > > > > Add clock drivers for MT8365 SoC. > > > > Signed-off-by: Fabien Parent > > Signed-off-by: Markus Schneider-Pargmann > > --- > > > > Notes: > > Changes in v3: > > - Changed all Kconfig options to be tristate > > - Do not depend on ARM64 > > - Fix order of frees on probe errors. > > - Use mtk_clk_register_gates_with_dev > > - Fixed null clocks > > - Removed clk26m_ck > > - Use MUX_GATE_CLR_SET_UPD instead of custom MT8365_MUX_CLR_SET_UPD > > - Use devm_clk_hw_register_mux for top_misc_muxes > > - Use devm_clk_hw_register_gate for peri_clks and top_clks > > - Fix checkpatch warnings > > - Add missing MODULE_LICENSEs in all files > > > > drivers/clk/mediatek/Kconfig | 50 + > > drivers/clk/mediatek/Makefile | 7 + > > drivers/clk/mediatek/clk-mt8365-apu.c | 55 + > > drivers/clk/mediatek/clk-mt8365-cam.c | 57 + > > drivers/clk/mediatek/clk-mt8365-mfg.c | 63 + > > drivers/clk/mediatek/clk-mt8365-mm.c | 112 ++ > > drivers/clk/mediatek/clk-mt8365-vdec.c | 63 + > > drivers/clk/mediatek/clk-mt8365-venc.c | 52 + > > drivers/clk/mediatek/clk-mt8365.c | 1155 +++++++++++++++++ > > .../dt-bindings/clock/mediatek,mt8365-clk.h | 179 ++- > > No, bindings are always separate. Of course, I screwed up my rebasing here, sorry. Fixed for v4. Best, Markus