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From:   Ayan Kumar Halder <ayankuma@amd.com>
To:     <stefano.stabellini@xilinx.com>, <sstabellini@kernel.org>,
        <julien@xen.org>, <bertrand.marquis@arm.com>,
        <mark.rutland@arm.com>, <maz@kernel.org>,
        <daniel.lezcano@linaro.org>, <tglx@linutronix.de>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        Ayan Kumar Halder <ayankuma@amd.com>
Subject: [PATCH v1] arm: clocksource: Check if timer is enabled for timer irq
Date:   Thu, 11 Aug 2022 10:36:20 +0100
Message-ID: <20220811093620.16680-1-ayankuma@amd.com>
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Refer ARM DDI 0487G.b, CNTP_CTL_EL0,
ISTATUS, bit [2] - When the value of the ENABLE bit is 1, ISTATUS
indicates whether the timer condition is met.

Thus, one need to check ENABLE bit along with ISTATUS, to confirm
whether the timer condition is met. Further as the doc says,
"When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN."

Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
---

Please refer to https://lore.kernel.org/all/6cfcd4fa-3afd-1c70-6a70-9df557ee1811@xen.org/T/
for the previous discussion on this issue on xen-devel mailing list.

 drivers/clocksource/arm_arch_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 9ab8221ee3c6..96921772814c 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -647,7 +647,7 @@ static __always_inline irqreturn_t timer_handler(const int access,
 	unsigned long ctrl;
 
 	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
-	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
+	if ((ctrl & ARCH_TIMER_CTRL_IT_STAT) && (ctrl & ARCH_TIMER_CTRL_ENABLE)) {
 		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 		evt->event_handler(evt);
-- 
2.17.1