Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20220726180623.1668-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <952a85ec-d1e9-7c14-6404-bc087723252f@linaro.org> <CA+V-a8vb+za1Zckk5aTxz0hKkd5fHQk7gtfV+HR_2YMZ5JuJEQ@mail.gmail.com>
 <3e3c0c80-48eb-098d-977d-a1801036fc0c@linaro.org> <CA+V-a8tJVGz57FcJVnbksMot=pg5dXALo4QEyqO+57HnOTJLfQ@mail.gmail.com>
 <CAMuHMdWih6XiVfLT0g=k8QrMmVzb2sqv9hxqtGE1t1F1Jvj_QA@mail.gmail.com>
In-Reply-To: <CAMuHMdWih6XiVfLT0g=k8QrMmVzb2sqv9hxqtGE1t1F1Jvj_QA@mail.gmail.com>
From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Fri, 12 Aug 2022 00:37:42 +0100
Message-ID: <CA+V-a8tkRJrugewfAunO7CP9H7A8H5OM2=uRQtDfk7=15Zkw4A@mail.gmail.com>
Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for
 RISC-V arch
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Anup Patel <anup@brainfault.org>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        LKML <linux-kernel@vger.kernel.org>,
        Biju Das <biju.das.jz@bp.renesas.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

Hi Geert,

On Thu, Aug 11, 2022 at 4:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> > > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > > <krzysztof.kozlowski@linaro.org> wrote:
> > > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > > >>> (RISC-V arch).
> > > >>>
> > > >>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >>> ---
> > > >>>  Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > > >>>  1 file changed, 9 insertions(+)
> > > >>>
> > > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> index ff80152f092f..f646df1a23af 100644
> > > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > > >>>  maintainers:
> > > >>>    - Geert Uytterhoeven <geert+renesas@glider.be>
> > > >>>
> > > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > > >>> +select:
> > > >>> +  not:
> > > >>> +    properties:
> > > >>> +      compatible:
> > > >>> +        contains:
> > > >>> +          items:
> > > >>> +            - const: renesas,r9a07g043f01
> > > >>
> > > >> Second issue - why not renesas,r9a07g043?
> > > >>
> > > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > > >
> > > > RZ/G2UL ARM64:
> > > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > > >
> > > > RZ/Five RISCV:
> > > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > > >
> > > > So to differentiate in ARM schema I am using  renesas,r9a07g043f01.
> > >
> > > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > > compatible at all, so they must not use the same fallback.
> > >
> > Agreed, I wanted to keep it consistent with what was done with ARM64
> > (since both the SoCs shared R9A07G043 part number).
> >
> > Geert - What are your thoughts on the above?
>
> "renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
> "renesas,r9a07g043f01", "renesas,r9a07g043u11", and
> "renesas,r9a07g043u12" are SoCs built by integrating one or more
> RV64 or ARM64 CPU cores and the related interrupt controllers with
> the CPU-less SoC base.
>
That's bang on! which I missed to convenience the DT maintainers.

Cheers,
Prabhakar