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Subject: Re: [PATCH] perf: riscv: fix broken build due to struct redefinition
From:   Jessica Clarke <jrtc27@jrtc27.com>
In-Reply-To: <20220812135119.1648940-1-conor.dooley@microchip.com>
Date:   Fri, 12 Aug 2022 15:13:54 +0100
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Palmer Dabbelt <palmer@rivosinc.com>,
        Atish Patra <atishp@atishpatra.org>,
        Anup Patel <anup@brainfault.org>,
        Will Deacon <will@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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Message-Id: <2055040C-D443-47FD-B6E2-C4C6B3E600B4@jrtc27.com>
References: <20220812135119.1648940-1-conor.dooley@microchip.com>
To:     Conor Dooley <conor.dooley@microchip.com>
Precedence: bulk

On 12 Aug 2022, at 14:51, Conor Dooley <conor.dooley@microchip.com> =
wrote:
>=20
> Building riscv/for-next produces following error:
> drivers/perf/riscv_pmu_sbi.c:44:7: error: redefinition of =
'sbi_pmu_ctr_info'
> union sbi_pmu_ctr_info {
>      ^
> arch/riscv/include/asm/sbi.h:125:7: note: previous definition is here
> union sbi_pmu_ctr_info {
>=20
> This appears to have been caused by a merge conflict resolution =
between
> riscv/for-next & riscv/fixes, causing the struct define not being

union, not struct

Jess

> properly moved to its header.
>=20
> Fixes: 9a7ccac63f9c ("perf: riscv_pmu{,_sbi}: Miscallenous improvement =
& fixes")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> drivers/perf/riscv_pmu_sbi.c | 14 --------------
> 1 file changed, 14 deletions(-)
>=20
> diff --git a/drivers/perf/riscv_pmu_sbi.c =
b/drivers/perf/riscv_pmu_sbi.c
> index e7c6fecbf061..6f6681bbfd36 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -41,20 +41,6 @@ static const struct attribute_group =
*riscv_pmu_attr_groups[] =3D {
> 	NULL,
> };
>=20
> -union sbi_pmu_ctr_info {
> -	unsigned long value;
> -	struct {
> -		unsigned long csr:12;
> -		unsigned long width:6;
> -#if __riscv_xlen =3D=3D 32
> -		unsigned long reserved:13;
> -#else
> -		unsigned long reserved:45;
> -#endif
> -		unsigned long type:1;
> -	};
> -};
> -
> /*
>  * RISC-V doesn't have hetergenous harts yet. This need to be part of
>  * per_cpu in case of harts with different pmu counters
> --=20
> 2.36.1
>=20
>=20
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