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Date:   Mon, 15 Aug 2022 20:37:25 +0300
From:   "Kirill A. Shutemov" <kirill@shutemov.name>
To:     Peter Zijlstra <peterz@infradead.org>
Cc:     "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andy Lutomirski <luto@kernel.org>, x86@kernel.org,
        Kostya Serebryany <kcc@google.com>,
        Andrey Ryabinin <ryabinin.a.a@gmail.com>,
        Andrey Konovalov <andreyknvl@gmail.com>,
        Alexander Potapenko <glider@google.com>,
        Taras Madan <tarasmadan@google.com>,
        Dmitry Vyukov <dvyukov@google.com>,
        "H . J . Lu" <hjl.tools@gmail.com>,
        Andi Kleen <ak@linux.intel.com>,
        Rick Edgecombe <rick.p.edgecombe@intel.com>,
        linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCHv6 04/11] x86/mm: Handle LAM on context switch
Message-ID: <20220815173725.ph6ogtqneiqwqek7@box.shutemov.name>
References: <20220815041803.17954-1-kirill.shutemov@linux.intel.com>
 <20220815041803.17954-5-kirill.shutemov@linux.intel.com>
 <YvpNQSEtu+Tbqrpd@worktop.programming.kicks-ass.net>
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On Mon, Aug 15, 2022 at 03:42:25PM +0200, Peter Zijlstra wrote:
> On Mon, Aug 15, 2022 at 07:17:56AM +0300, Kirill A. Shutemov wrote:
> > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> > index c1e31e9a85d7..fdc0b69b5da7 100644
> > --- a/arch/x86/mm/tlb.c
> > +++ b/arch/x86/mm/tlb.c
> > @@ -154,17 +154,18 @@ static inline u16 user_pcid(u16 asid)
> >  	return ret;
> >  }
> >  
> > -static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
> > +static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
> >  {
> >  	if (static_cpu_has(X86_FEATURE_PCID)) {
> > -		return __sme_pa(pgd) | kern_pcid(asid);
> > +		return __sme_pa(pgd) | kern_pcid(asid) | lam;
> >  	} else {
> >  		VM_WARN_ON_ONCE(asid != 0);
> > -		return __sme_pa(pgd);
> > +		return __sme_pa(pgd) | lam;
> >  	}
> >  }
> >  
> > -static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
> > +static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
> > +					      unsigned long lam)
> >  {
> >  	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
> >  	/*
> > @@ -173,7 +174,7 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
> >  	 * boot because all CPU's the have same capabilities:
> >  	 */
> >  	VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
> > -	return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
> > +	return __sme_pa(pgd) | kern_pcid(asid) | lam | CR3_NOFLUSH;
> >  }
> 
> Looking at this; I wonder if we want something like this:
> 
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c
> @@ -157,6 +157,7 @@ static inline u16 user_pcid(u16 asid)
>  static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
>  {
>  	if (static_cpu_has(X86_FEATURE_PCID)) {
> +		VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>  		return __sme_pa(pgd) | kern_pcid(asid) | lam;
>  	} else {
>  		VM_WARN_ON_ONCE(asid != 0);
> @@ -167,14 +168,13 @@ static inline unsigned long build_cr3(pg
>  static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
>  					      unsigned long lam)
>  {
> -	VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>  	/*
>  	 * Use boot_cpu_has() instead of this_cpu_has() as this function
>  	 * might be called during early boot. This should work even after
>  	 * boot because all CPU's the have same capabilities:
>  	 */
>  	VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
> -	return __sme_pa(pgd) | kern_pcid(asid) | lam | CR3_NOFLUSH;
> +	return build_cr3(pgd, asid, lam) | CR3_NOFLUSH;
>  }

Looks sane, but seems unrelated to the patch. Is it okay to fold it
anyway?

-- 
  Kiryl Shutsemau / Kirill A. Shutemov