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References: <20220729100524.387-1-chevron.li@bayhubtech.com>
In-Reply-To: <20220729100524.387-1-chevron.li@bayhubtech.com>
From:   Ulf Hansson <ulf.hansson@linaro.org>
Date:   Mon, 15 Aug 2022 20:27:54 +0200
Message-ID: <CAPDyKFqGhgiAwzsia7aXO8Rb+1xYwfQDtLRj0ArncX=Qt8Tg1A@mail.gmail.com>
Subject: Re: [PATCH V2 1/1] mmc: sdhci-pci-o2micro: fix some SD cards
 compatibility issue at DDR50 mode
To:     Chevron Li <chevron.li@bayhubtech.com>
Cc:     adrian.hunter@intel.com, linux-mmc@vger.kernel.org,
        linux-kernel@vger.kernel.org, shaper.liu@bayhubtech.com,
        shirley.her@bayhubtech.com, xiaoguang.yu@bayhubtech.com
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Precedence: bulk

On Fri, 29 Jul 2022 at 12:05, Chevron Li <chevron.li@bayhubtech.com> wrote:
>
> Bayhub chips have better compatibility support for SDR50 than DDR50
> and both mode have the same R/W performance when clock frequency >= 100MHz.
> Disable DDR50 mode and use SDR50 instead.
>
> Signed-off-by: Chevron Li <chevron.li@bayhubtech.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
> Changes on V1:
> 1.Set quirks2 flag SDHCI_QUIRK2_BROKEN_DDR50 for bayhub chips.
> 2.Use bayhub hardware input tuning for SDR50 mode instead of standard tuning flow.
>
> Changes on V2:
> Update commit format and information.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 0d4d343dbb77..ad457cd9cbaa 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -317,11 +317,12 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>         u32 reg_val;
>
>         /*
> -        * This handler only implements the eMMC tuning that is specific to
> +        * This handler implements the hardware tuning that is specific to
>          * this controller.  Fall back to the standard method for other TIMING.
>          */
>         if ((host->timing != MMC_TIMING_MMC_HS200) &&
> -               (host->timing != MMC_TIMING_UHS_SDR104))
> +               (host->timing != MMC_TIMING_UHS_SDR104) &&
> +               (host->timing != MMC_TIMING_UHS_SDR50))
>                 return sdhci_execute_tuning(mmc, opcode);
>
>         if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
> @@ -631,6 +632,8 @@ static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
>                 if (reg & 0x1)
>                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
>
> +               host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
> +
>                 sdhci_pci_o2_enable_msi(chip, host);
>
>                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
>
> base-commit: 68e77ffbfd06ae3ef8f2abf1c3b971383c866983
> --
> 2.32.0
>